diff options
| author | Hal Finkel <hfinkel@anl.gov> | 2013-07-11 16:31:51 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2013-07-11 16:31:51 +0000 |
| commit | 53c86db25b5b4e163c68dc91c8ce1bc8180e6ff3 (patch) | |
| tree | d9bf3b90cb52e3158ff8862d824c8fd7ab8dde6f /lib/Target/PowerPC/PPCISelDAGToDAG.cpp | |
| parent | 9e639e8fd95488cb4c8ef2f7f3a41919acb29ac4 (diff) | |
| download | llvm-53c86db25b5b4e163c68dc91c8ce1bc8180e6ff3.tar.gz llvm-53c86db25b5b4e163c68dc91c8ce1bc8180e6ff3.tar.bz2 llvm-53c86db25b5b4e163c68dc91c8ce1bc8180e6ff3.tar.xz | |
PPCDAGToDAGISel::isRunOfOnes should return false on zero
This fixes a bug (found by csmith) at -O0 where we attempt to create a RLWIMI
with an out-of-range operand. Most uses of the isRunOfOnes function are guarded
by a condition that the value is not zero. This was not true in two places, and
in both places a zero input would result in an out-of-rage MB value (= 32).
To fix this, isRunOfOnes returns false on a zero input (and I've remove one
now-redundant guard).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186101 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCISelDAGToDAG.cpp')
| -rw-r--r-- | lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index 901d369097..475bde18ef 100644 --- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -330,6 +330,9 @@ static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) { } bool PPCDAGToDAGISel::isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) { + if (!Val) + return false; + if (isShiftedMask_32(Val)) { // look for the first non-zero bit MB = countLeadingZeros(Val); @@ -435,7 +438,7 @@ SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) { } unsigned MB, ME; - if (InsertMask && isRunOfOnes(InsertMask, MB, ME)) { + if (isRunOfOnes(InsertMask, MB, ME)) { SDValue Tmp1, Tmp2; if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) && |