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author | Chris Lattner <sabre@nondot.org> | 2006-11-14 05:28:08 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2006-11-14 05:28:08 +0000 |
commit | ac011bce9e8a69f99f92d46133adbf883a91cb6f (patch) | |
tree | 34da12c0a906915f3c2a4d720abc7c197a33d580 /lib/Target/PowerPC/PPCISelLowering.cpp | |
parent | 472c7918b0bc155e002db6f682c899e21bff852c (diff) | |
download | llvm-ac011bce9e8a69f99f92d46133adbf883a91cb6f.tar.gz llvm-ac011bce9e8a69f99f92d46133adbf883a91cb6f.tar.bz2 llvm-ac011bce9e8a69f99f92d46133adbf883a91cb6f.tar.xz |
lower "X = seteq Y, Z" to '(shr (ctlz (xor Y, Z)), 5)' instead of
'(shr (ctlz (sub Y, Z)), 5)'.
The use of xor better exposes the operation to bit-twiddling logic in the
dag combiner. For example, this:
typedef struct {
unsigned prefix : 4;
unsigned code : 4;
unsigned unsigned_p : 4;
} tree_common;
int foo(tree_common *a, tree_common *b) {
return a->code == b->code;
}
Now compiles to:
_foo:
lwz r2, 0(r4)
lwz r3, 0(r3)
xor r2, r3, r2
rlwinm r2, r2, 28, 28, 31
cntlzw r2, r2
srwi r3, r2, 5
blr
instead of:
_foo:
lbz r2, 3(r4)
lbz r3, 3(r3)
srwi r2, r2, 4
srwi r3, r3, 4
subf r2, r2, r3
cntlzw r2, r2
srwi r3, r2, 5
blr
saving a cycle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31725 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCISelLowering.cpp')
-rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.cpp | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 066fd191c9..e2419298b5 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -1038,12 +1038,14 @@ static SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG) { } // If we have an integer seteq/setne, turn it into a compare against zero - // by subtracting the rhs from the lhs, which is faster than setting a - // condition register, reading it back out, and masking the correct bit. + // by xor'ing the rhs with the lhs, which is faster than setting a + // condition register, reading it back out, and masking the correct bit. The + // normal approach here uses sub to do this instead of xor. Using xor exposes + // the result to other bit-twiddling opportunities. MVT::ValueType LHSVT = Op.getOperand(0).getValueType(); if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) { MVT::ValueType VT = Op.getValueType(); - SDOperand Sub = DAG.getNode(ISD::SUB, LHSVT, Op.getOperand(0), + SDOperand Sub = DAG.getNode(ISD::XOR, LHSVT, Op.getOperand(0), Op.getOperand(1)); return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC); } |