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| author | Hal Finkel <hfinkel@anl.gov> | 2013-03-31 01:58:02 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2013-03-31 01:58:02 +0000 |
| commit | 9ad0f4907b3ba0916a8b6cdb95d298d2ddb7d405 (patch) | |
| tree | 95b16c768d1a5e1d043d3459b352fd34a665076b /lib/Target/PowerPC/PPCISelLowering.h | |
| parent | 0b68b758bbb6718fc67423109eeb9df64c711a37 (diff) | |
| download | llvm-9ad0f4907b3ba0916a8b6cdb95d298d2ddb7d405.tar.gz llvm-9ad0f4907b3ba0916a8b6cdb95d298d2ddb7d405.tar.bz2 llvm-9ad0f4907b3ba0916a8b6cdb95d298d2ddb7d405.tar.xz | |
Cleanup PPC(64) i32 -> float/double conversion
The existing SINT_TO_FP code for i32 -> float/double conversion was disabled
because it relied on broken EXTSW_32/STD_32 instruction definitions. The
original intent had been to enable these 64-bit instructions to be used on CPUs
that support them even in 32-bit mode. Unfortunately, this form of lying to
the infrastructure was buggy (as explained in the FIXME comment) and had
therefore been disabled.
This re-enables this functionality, using regular DAG nodes, but only when
compiling in 64-bit mode. The old STD_32/EXTSW_32 definitions (which were dead)
are removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178438 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCISelLowering.h')
| -rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.h | 9 |
1 files changed, 1 insertions, 8 deletions
diff --git a/lib/Target/PowerPC/PPCISelLowering.h b/lib/Target/PowerPC/PPCISelLowering.h index 6296400ec7..bce05a16c6 100644 --- a/lib/Target/PowerPC/PPCISelLowering.h +++ b/lib/Target/PowerPC/PPCISelLowering.h @@ -91,10 +91,6 @@ namespace llvm { /// code. SRL, SRA, SHL, - /// EXTSW_32 - This is the EXTSW instruction for use with "32-bit" - /// registers. - EXTSW_32, - /// CALL - A direct function call. /// CALL_NOP is a call with the special NOP which follows 64-bit /// SVR4 calls. @@ -234,14 +230,11 @@ namespace llvm { /// optimizations due to constant folding. VADD_SPLAT, - /// STD_32 - This is the STD instruction for use with "32-bit" registers. - STD_32 = ISD::FIRST_TARGET_MEMORY_OPCODE, - /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a /// byte-swapping store instruction. It byte-swaps the low "Type" bits of /// the GPRC input, then stores it through Ptr. Type can be either i16 or /// i32. - STBRX, + STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE, /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a /// byte-swapping load instruction. It loads "Type" bits, byte swaps it, |