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| author | Bill Schmidt <wschmidt@linux.vnet.ibm.com> | 2013-06-12 16:39:22 +0000 |
|---|---|---|
| committer | Bill Schmidt <wschmidt@linux.vnet.ibm.com> | 2013-06-12 16:39:22 +0000 |
| commit | d3f7766f2363862b9c8586d2f78bc413223240d3 (patch) | |
| tree | 0409cfb12922b7498dcd93280edf57cd03c91312 /lib/Target/PowerPC/PPCISelLowering.h | |
| parent | 6d6cbe3a3aef168c9ccbbde0d834b9618aa5829f (diff) | |
| download | llvm-d3f7766f2363862b9c8586d2f78bc413223240d3.tar.gz llvm-d3f7766f2363862b9c8586d2f78bc413223240d3.tar.bz2 llvm-d3f7766f2363862b9c8586d2f78bc413223240d3.tar.xz | |
[PowerPC] Expose some calling convention functions in PPCISelLowering.h.
This is a preparatory patch for fast-isel support. The instruction
selector will need to access some functions in PPCGenCallingConv.inc,
which in turn requires several helper functions to be defined. These
are currently defined near the only use of PCCGenCallingConv.inc,
inside PPCISelLowering.cpp. This patch moves the declaration of the
functions into the associated header file to provide the needed
visibility.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183844 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCISelLowering.h')
| -rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.h | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/lib/Target/PowerPC/PPCISelLowering.h b/lib/Target/PowerPC/PPCISelLowering.h index ca90e79dab..e85f96c38d 100644 --- a/lib/Target/PowerPC/PPCISelLowering.h +++ b/lib/Target/PowerPC/PPCISelLowering.h @@ -20,6 +20,7 @@ #include "PPCRegisterInfo.h" #include "PPCSubtarget.h" #include "llvm/CodeGen/SelectionDAG.h" +#include "llvm/CodeGen/CallingConvLower.h" #include "llvm/Target/TargetLowering.h" namespace llvm { @@ -621,6 +622,23 @@ namespace llvm { SDValue DAGCombineFastRecip(SDValue Op, DAGCombinerInfo &DCI) const; SDValue DAGCombineFastRecipFSQRT(SDValue Op, DAGCombinerInfo &DCI) const; }; + + bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT, + CCValAssign::LocInfo &LocInfo, + ISD::ArgFlagsTy &ArgFlags, + CCState &State); + + bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT, + MVT &LocVT, + CCValAssign::LocInfo &LocInfo, + ISD::ArgFlagsTy &ArgFlags, + CCState &State); + + bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT, + MVT &LocVT, + CCValAssign::LocInfo &LocInfo, + ISD::ArgFlagsTy &ArgFlags, + CCState &State); } #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H |