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| author | Chris Lattner <sabre@nondot.org> | 2006-03-22 05:30:33 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2006-03-22 05:30:33 +0000 |
| commit | ecfe55e65b6a72fddd543c42f2e2df4c96c647ba (patch) | |
| tree | f1b6b27e1a10ef71ed8433fce838e2c9519658e3 /lib/Target/PowerPC/PPCISelLowering.h | |
| parent | e5ba580ab05b18eaa9fd4d36e31466e41f693ad9 (diff) | |
| download | llvm-ecfe55e65b6a72fddd543c42f2e2df4c96c647ba.tar.gz llvm-ecfe55e65b6a72fddd543c42f2e2df4c96c647ba.tar.bz2 llvm-ecfe55e65b6a72fddd543c42f2e2df4c96c647ba.tar.xz | |
When possible, custom lower 32-bit SINT_TO_FP to this:
_foo2:
extsw r2, r3
std r2, -8(r1)
lfd f0, -8(r1)
fcfid f0, f0
frsp f1, f0
blr
instead of this:
_foo2:
lis r2, ha16(LCPI2_0)
lis r4, 17200
xoris r3, r3, 32768
stw r3, -4(r1)
stw r4, -8(r1)
lfs f0, lo16(LCPI2_0)(r2)
lfd f1, -8(r1)
fsub f0, f1, f0
frsp f1, f0
blr
This speeds up Misc/pi from 2.44s->2.09s with LLC and from 3.01->2.18s
with llcbeta (16.7% and 38.1% respectively).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26943 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCISelLowering.h')
| -rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/lib/Target/PowerPC/PPCISelLowering.h b/lib/Target/PowerPC/PPCISelLowering.h index cf7ebc4824..abf7a79db8 100644 --- a/lib/Target/PowerPC/PPCISelLowering.h +++ b/lib/Target/PowerPC/PPCISelLowering.h @@ -75,7 +75,14 @@ namespace llvm { /// shift amounts. These nodes are generated by the multi-precision shift /// code. SRL, SRA, SHL, + + /// EXTSW_32 - This is the EXTSW instruction for use with "32-bit" + /// registers. + EXTSW_32, + /// STD_32 - This is the STD instruction for use with "32-bit" registers. + STD_32, + /// CALL - A function call. CALL, |