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| author | Chris Lattner <sabre@nondot.org> | 2006-04-12 16:53:28 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2006-04-12 16:53:28 +0000 |
| commit | 2b1c3258d68271098172e52d4e1f8424d855025f (patch) | |
| tree | 99e31b9f7bbf8ae11b21976ab022b1905efa0732 /lib/Target/PowerPC/PPCInstrAltivec.td | |
| parent | 8e7401e52f3938a775819e8a6de095ecf7dbad92 (diff) | |
| download | llvm-2b1c3258d68271098172e52d4e1f8424d855025f.tar.gz llvm-2b1c3258d68271098172e52d4e1f8424d855025f.tar.bz2 llvm-2b1c3258d68271098172e52d4e1f8424d855025f.tar.xz | |
Ensure that zero vectors are always v4i32, which forces them to CSE with
each other. This implements CodeGen/PowerPC/vxor-canonicalize.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27609 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCInstrAltivec.td')
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrAltivec.td | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/lib/Target/PowerPC/PPCInstrAltivec.td b/lib/Target/PowerPC/PPCInstrAltivec.td index 8377077303..39304c876f 100644 --- a/lib/Target/PowerPC/PPCInstrAltivec.td +++ b/lib/Target/PowerPC/PPCInstrAltivec.td @@ -521,7 +521,7 @@ def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>; def V_SET0 : VXForm_setzero<1220, (ops VRRC:$vD), "vxor $vD, $vD, $vD", VecFP, - [(set VRRC:$vD, (v4f32 immAllZerosV))]>; + [(set VRRC:$vD, (v4i32 immAllZerosV))]>; } //===----------------------------------------------------------------------===// @@ -544,9 +544,6 @@ def : Pat<(int_ppc_altivec_dststt GPRC:$rA, GPRC:$rB, imm:$STRM), def : Pat<(v16i8 (undef)), (v16i8 (IMPLICIT_DEF_VRRC))>; def : Pat<(v8i16 (undef)), (v8i16 (IMPLICIT_DEF_VRRC))>; def : Pat<(v4i32 (undef)), (v4i32 (IMPLICIT_DEF_VRRC))>; -def : Pat<(v16i8 immAllZerosV), (v16i8 (V_SET0))>; -def : Pat<(v8i16 immAllZerosV), (v8i16 (V_SET0))>; -def : Pat<(v4i32 immAllZerosV), (v4i32 (V_SET0))>; // Loads. def : Pat<(v16i8 (load xoaddr:$src)), (v16i8 (LVX xoaddr:$src))>; @@ -637,7 +634,7 @@ def : Pat<(v8i16 (and VRRC:$A, (vnot VRRC:$B))), (v8i16 (VANDC VRRC:$A, VRRC:$B))>; def : Pat<(fmul VRRC:$vA, VRRC:$vB), - (VMADDFP VRRC:$vA, VRRC:$vB, (V_SET0))>; + (VMADDFP VRRC:$vA, VRRC:$vB, (v4i32 (V_SET0)))>; // Fused multiply add and multiply sub for packed float. These are represented // separately from the real instructions above, for operations that must have |