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| author | Chris Lattner <sabre@nondot.org> | 2006-04-05 22:27:14 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2006-04-05 22:27:14 +0000 |
| commit | d8242b49b24a46f685599834b6ca33dfbeba9382 (patch) | |
| tree | 784666135db15210802a6f9301fa33b5a48f31aa /lib/Target/PowerPC/PPCInstrAltivec.td | |
| parent | 20a86db26a94ca6ca61baa11176c07b8c61e4b01 (diff) | |
| download | llvm-d8242b49b24a46f685599834b6ca33dfbeba9382.tar.gz llvm-d8242b49b24a46f685599834b6ca33dfbeba9382.tar.bz2 llvm-d8242b49b24a46f685599834b6ca33dfbeba9382.tar.xz | |
Add all of the data stream intrinsics and instructions. woo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27442 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCInstrAltivec.td')
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrAltivec.td | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/lib/Target/PowerPC/PPCInstrAltivec.td b/lib/Target/PowerPC/PPCInstrAltivec.td index 4c297bd178..6cac3ec40d 100644 --- a/lib/Target/PowerPC/PPCInstrAltivec.td +++ b/lib/Target/PowerPC/PPCInstrAltivec.td @@ -93,6 +93,15 @@ class VX2_Int<bits<11> xo, string opc, Intrinsic IntID> def IMPLICIT_DEF_VRRC : Pseudo<(ops VRRC:$rD), "; $rD = IMPLICIT_DEF_VRRC", [(set VRRC:$rD, (v4f32 (undef)))]>; +let noResults = 1 in { +def DSS : DSS_Form<822, (ops u5imm:$A, u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2), + "dss $STRM, $A", LdStGeneral /*FIXME*/, []>; +def DST : DSS_Form<342, (ops u5imm:$T, u5imm:$STRM, GPRC:$rA, GPRC:$rB), + "dst $rA, $rB, $STRM, $T", LdStGeneral /*FIXME*/, []>; +def DSTST : DSS_Form<374, (ops u5imm:$T, u5imm:$STRM, GPRC:$rA, GPRC:$rB), + "dstst $rA, $rB, $STRM, $T", LdStGeneral /*FIXME*/, []>; +} + def MFVSCR : VXForm_4<1540, (ops VRRC:$vD), "mfvcr $vD", LdStGeneral, [(set VRRC:$vD, (int_ppc_altivec_mfvscr))]>; @@ -431,6 +440,18 @@ def V_SET0 : VXForm_setzero<1220, (ops VRRC:$vD), // Additional Altivec Patterns // +// DS* intrinsics. +def : Pat<(int_ppc_altivec_dss imm:$STRM), (DSS 0, imm:$STRM, 0, 0)>; +def : Pat<(int_ppc_altivec_dssall), (DSS 1, 0, 0, 0)>; +def : Pat<(int_ppc_altivec_dst GPRC:$rA, GPRC:$rB, imm:$STRM), + (DST 0, imm:$STRM, GPRC:$rA, GPRC:$rB)>; +def : Pat<(int_ppc_altivec_dstt GPRC:$rA, GPRC:$rB, imm:$STRM), + (DST 1, imm:$STRM, GPRC:$rA, GPRC:$rB)>; +def : Pat<(int_ppc_altivec_dstst GPRC:$rA, GPRC:$rB, imm:$STRM), + (DSTST 0, imm:$STRM, GPRC:$rA, GPRC:$rB)>; +def : Pat<(int_ppc_altivec_dststt GPRC:$rA, GPRC:$rB, imm:$STRM), + (DSTST 1, imm:$STRM, GPRC:$rA, GPRC:$rB)>; + // Undef/Zero. def : Pat<(v16i8 (undef)), (v16i8 (IMPLICIT_DEF_VRRC))>; def : Pat<(v8i16 (undef)), (v8i16 (IMPLICIT_DEF_VRRC))>; |