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author | Nate Begeman <natebegeman@mac.com> | 2005-11-23 05:29:52 +0000 |
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committer | Nate Begeman <natebegeman@mac.com> | 2005-11-23 05:29:52 +0000 |
commit | e4f17a5f9b6b5c94dccfd14babcf58d9d5dab4e8 (patch) | |
tree | fcf31435fbd9c62464ffa34fff58762a1ed18769 /lib/Target/PowerPC/PPCInstrFormats.td | |
parent | 7c0c5670588e39222bb039755cdf9030ab17c64e (diff) | |
download | llvm-e4f17a5f9b6b5c94dccfd14babcf58d9d5dab4e8.tar.gz llvm-e4f17a5f9b6b5c94dccfd14babcf58d9d5dab4e8.tar.bz2 llvm-e4f17a5f9b6b5c94dccfd14babcf58d9d5dab4e8.tar.xz |
Some first bits of AltiVec stuff: Instruction Formats, Encodings, and
Registers. Apologies to Jim if the scheduling info so far isn't accurate.
There's a few more things like VRsave support that need to be finished up
in my local tree before I can commit code that Does The Right Thing for
turning 4 x float into the various altivec packed float instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24489 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCInstrFormats.td')
-rw-r--r-- | lib/Target/PowerPC/PPCInstrFormats.td | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td index 2ec71532d8..8f93ac9fd3 100644 --- a/lib/Target/PowerPC/PPCInstrFormats.td +++ b/lib/Target/PowerPC/PPCInstrFormats.td @@ -548,6 +548,51 @@ class MDForm_1<bits<6> opcode, bits<3> xo, dag OL, string asmstr, let Inst{31} = RC; } +// E-1 VA-Form +class VAForm_1<bits<6> xo, dag OL, string asmstr, + InstrItinClass itin, list<dag> pattern> + : I<4, OL, asmstr, itin> { + bits<5> VD; + bits<5> VA; + bits<5> VB; + bits<5> VC; + + let Inst{6-10} = VD; + let Inst{11-15} = VA; + let Inst{16-20} = VB; + let Inst{21-25} = VC; + let Inst{26-31} = xo; +} + +// E-2 VX-Form +class VXForm_1<bits<11> xo, dag OL, string asmstr, + InstrItinClass itin, list<dag> pattern> + : I<4, OL, asmstr, itin> { + bits<5> VD; + bits<5> VA; + bits<5> VB; + + let Inst{6-10} = VD; + let Inst{11-15} = VA; + let Inst{16-20} = VB; + let Inst{21-31} = xo; +} + +// E-4 VXR-Form +class VXRForm_1<bits<10> xo, bit rc, dag OL, string asmstr, + InstrItinClass itin, list<dag> pattern> + : I<4, OL, asmstr, itin> { + bits<5> VD; + bits<5> VA; + bits<5> VB; + + let Inst{6-10} = VD; + let Inst{11-15} = VA; + let Inst{16-20} = VB; + let Inst{21} = rc; + let Inst{22-31} = xo; +} + //===----------------------------------------------------------------------===// def NoItin : InstrItinClass; class Pseudo<dag OL, string asmstr, list<dag> pattern> |