convert PPC::BCC to use the 'pred' operand instead of separate predicate

value and CR reg #.  This requires swapping the order of these everywhere
that touches BCC and requires us to write custom matching logic for
PPCcondbranch :(


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31835 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 3 insertions, 3 deletions

diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp
index bee3238079..1bded0a243 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -260,13 +260,13 @@ void PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
       BuildMI(&MBB, PPC::B, 1).addMBB(TBB);
     else                // Conditional branch
       BuildMI(&MBB, PPC::BCC, 3)
-        .addReg(Cond[0].getReg()).addImm(Cond[1].getImm()).addMBB(TBB);
+        .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
     return;
   }
   
   // Two-way Conditional Branch.
   BuildMI(&MBB, PPC::BCC, 3)
-    .addReg(Cond[0].getReg()).addImm(Cond[1].getImm()).addMBB(TBB);
+    .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
   BuildMI(&MBB, PPC::B, 1).addMBB(FBB);
 }
 
@@ -285,6 +285,6 @@ bool PPCInstrInfo::
 ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
   assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
   // Leave the CR# the same, but invert the condition.
-  Cond[1].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[1].getImm()));
+  Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
   return false;
 }