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| author | Hal Finkel <hfinkel@anl.gov> | 2011-12-05 17:55:17 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2011-12-05 17:55:17 +0000 |
| commit | 3fd0018af1b692cabfa5a002bf41f1e756aa9dde (patch) | |
| tree | 7af1ee6eaa17a72254bd7860467313fa4c442ed2 /lib/Target/PowerPC/PPCInstrInfo.cpp | |
| parent | 9489487f9863ca9f0ae9b4572d206910f1c5a581 (diff) | |
| download | llvm-3fd0018af1b692cabfa5a002bf41f1e756aa9dde.tar.gz llvm-3fd0018af1b692cabfa5a002bf41f1e756aa9dde.tar.bz2 llvm-3fd0018af1b692cabfa5a002bf41f1e756aa9dde.tar.xz | |
enable PPC register scavenging by default (update tests and remove some FIXMEs)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145819 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCInstrInfo.cpp')
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrInfo.cpp | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp index cdb15a1755..f28d07c8a6 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -33,8 +33,8 @@ #include "PPCGenInstrInfo.inc" namespace llvm { -extern cl::opt<bool> EnablePPC32RS; // FIXME (64-bit): See PPCRegisterInfo.cpp. -extern cl::opt<bool> EnablePPC64RS; // FIXME (64-bit): See PPCRegisterInfo.cpp. +extern cl::opt<bool> DisablePPC32RS; +extern cl::opt<bool> DisablePPC64RS; } using namespace llvm; @@ -345,6 +345,7 @@ void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB, BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc)); } +// This function returns true if a CR spill is necessary and false otherwise. bool PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF, unsigned SrcReg, bool isKill, @@ -395,9 +396,8 @@ PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF, getKillRegState(isKill)), FrameIdx)); } else if (PPC::CRRCRegisterClass->hasSubClassEq(RC)) { - if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) || - (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) { - // FIXME (64-bit): Enable + if ((!DisablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) || + (!DisablePPC64RS && TM.getSubtargetImpl()->isPPC64())) { NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR)) .addReg(SrcReg, getKillRegState(isKill)), |