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author | Hal Finkel <hfinkel@anl.gov> | 2013-04-10 06:42:34 +0000 |
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committer | Hal Finkel <hfinkel@anl.gov> | 2013-04-10 06:42:34 +0000 |
commit | 90dd7fd167b6d09e4a7f37e35dcbfdc492546a79 (patch) | |
tree | 21572d743188d6c232746d0e7d75d7802b43b73c /lib/Target/PowerPC/PPCInstrInfo.cpp | |
parent | a2561a0153237291980722383f409a6499b12efc (diff) | |
download | llvm-90dd7fd167b6d09e4a7f37e35dcbfdc492546a79.tar.gz llvm-90dd7fd167b6d09e4a7f37e35dcbfdc492546a79.tar.bz2 llvm-90dd7fd167b6d09e4a7f37e35dcbfdc492546a79.tar.xz |
PPC: Prep for if conversion of bctr[l]
This adds in-principle support for if-converting the bctr[l] instructions.
These instructions are used for indirect branching. It seems, however, that the
current if converter will never actually predicate these. To do so, it would
need the ability to hoist a few setup insts. out of the conditionally-executed
block. For example, code like this:
void foo(int a, int (*bar)()) { if (a != 0) bar(); }
becomes:
...
beq 0, .LBB0_2
std 2, 40(1)
mr 12, 4
ld 3, 0(4)
ld 11, 16(4)
ld 2, 8(4)
mtctr 3
bctrl
ld 2, 40(1)
.LBB0_2:
...
and it would be safe to do all of this unconditionally with a predicated
beqctrl instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179156 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCInstrInfo.cpp')
-rw-r--r-- | lib/Target/PowerPC/PPCInstrInfo.cpp | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp index 51bc4f23cc..773b62326f 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -882,6 +882,10 @@ bool PPCInstrInfo::isPredicated(const MachineInstr *MI) const { default: return false; case PPC::BCC: + case PPC::BCCTR: + case PPC::BCCTR8: + case PPC::BCCTRL: + case PPC::BCCTRL8: case PPC::BCLR: case PPC::BDZLR: case PPC::BDZLR8: @@ -938,6 +942,19 @@ bool PPCInstrInfo::PredicateInstruction( } return true; + } else if (OpC == PPC::BCTR || OpC == PPC::BCTR8 || + OpC == PPC::BCTRL || OpC == PPC::BCTRL8) { + if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) + llvm_unreachable("Cannot predicate bctr[l] on the ctr register"); + + bool setLR = OpC == PPC::BCTRL || OpC == PPC::BCTRL8; + bool isPPC64 = TM.getSubtargetImpl()->isPPC64(); + MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8) : + (setLR ? PPC::BCCTRL : PPC::BCCTR))); + MachineInstrBuilder(*MI->getParent()->getParent(), MI) + .addImm(Pred[0].getImm()) + .addReg(Pred[1].getReg()); + return true; } return false; @@ -1009,6 +1026,10 @@ bool PPCInstrInfo::isPredicable(MachineInstr *MI) const { return false; case PPC::B: case PPC::BLR: + case PPC::BCTR: + case PPC::BCTR8: + case PPC::BCTRL: + case PPC::BCTRL8: return true; } } |