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author | Hal Finkel <hfinkel@anl.gov> | 2014-03-29 05:29:01 +0000 |
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committer | Hal Finkel <hfinkel@anl.gov> | 2014-03-29 05:29:01 +0000 |
commit | 44b2b9dc1a6192fda90990ec9eec922e3f8d2049 (patch) | |
tree | 799b084ff01548b0c8e4e2a051363a6a4ac11fde /lib/Target/PowerPC/PPCRegisterInfo.cpp | |
parent | c06afdcb65acd3f1fb28ce6280fed3a2d0db764c (diff) | |
download | llvm-44b2b9dc1a6192fda90990ec9eec922e3f8d2049.tar.gz llvm-44b2b9dc1a6192fda90990ec9eec922e3f8d2049.tar.bz2 llvm-44b2b9dc1a6192fda90990ec9eec922e3f8d2049.tar.xz |
[PowerPC] Add subregister classes for f64 VSX values
We had stored both f64 values and v2f64, etc. values in the VSX registers. This
worked, but was suboptimal because we would always spill 16-byte values even
through we almost always had scalar 8-byte values. This resulted in an
increase in stack-size use, extra memory bandwidth, etc. To fix this, I've
added 64-bit subregisters of the Altivec registers, and combined those with the
existing scalar floating-point registers to form a class of VSX scalar
floating-point registers. The ABI code has also been enhanced to use this
register class and some other necessary improvements have been made.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205075 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCRegisterInfo.cpp')
-rw-r--r-- | lib/Target/PowerPC/PPCRegisterInfo.cpp | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index c68e922355..78c5a124fb 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -229,16 +229,33 @@ PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, case PPC::F8RCRegClassID: case PPC::F4RCRegClassID: case PPC::VRRCRegClassID: + case PPC::VFRCRegClassID: case PPC::VSLRCRegClassID: case PPC::VSHRCRegClassID: return 32 - DefaultSafety; case PPC::VSRCRegClassID: + case PPC::VSFRCRegClassID: return 64 - DefaultSafety; case PPC::CRRCRegClassID: return 8 - DefaultSafety; } } +const TargetRegisterClass* +PPCRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)const { + if (Subtarget.hasVSX()) { + // With VSX, we can inflate various sub-register classes to the full VSX + // register set. + + if (RC == &PPC::F8RCRegClass) + return &PPC::VSFRCRegClass; + else if (RC == &PPC::VRRCRegClass) + return &PPC::VSRCRegClass; + } + + return TargetRegisterInfo::getLargestLegalSuperClass(RC); +} + //===----------------------------------------------------------------------===// // Stack Frame Processing methods //===----------------------------------------------------------------------===// |