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author | Bill Wendling <isanbard@gmail.com> | 2008-03-10 22:49:16 +0000 |
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committer | Bill Wendling <isanbard@gmail.com> | 2008-03-10 22:49:16 +0000 |
commit | 4a66e9a57e679b4f3243bf2061daf53c70102030 (patch) | |
tree | ac34b8a648633889b08543c125de72998d31e8cf /lib/Target/PowerPC/PPCRegisterInfo.cpp | |
parent | ed61c0bc76a7b9001d7639a908c955d0fae35bac (diff) | |
download | llvm-4a66e9a57e679b4f3243bf2061daf53c70102030.tar.gz llvm-4a66e9a57e679b4f3243bf2061daf53c70102030.tar.bz2 llvm-4a66e9a57e679b4f3243bf2061daf53c70102030.tar.xz |
Change the "enable/disable" mechanism so that we can enable PPC register
scavenging for 32-bit and 64-bit separately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48186 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCRegisterInfo.cpp')
-rw-r--r-- | lib/Target/PowerPC/PPCRegisterInfo.cpp | 31 |
1 files changed, 19 insertions, 12 deletions
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index 90c3282978..cc865b4fb1 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -43,15 +43,22 @@ using namespace llvm; // FIXME (64-bit): Eventually enable by default. -cl::opt<bool> EnablePPCRS("enable-ppc-regscavenger", - cl::init(false), - cl::desc("enable PPC register scavenger"), - cl::Hidden); +cl::opt<bool> EnablePPC32RS("enable-ppc32-regscavenger", + cl::init(false), + cl::desc("Enable PPC32 register scavenger"), + cl::Hidden); +cl::opt<bool> EnablePPC64RS("enable-ppc64-regscavenger", + cl::init(false), + cl::desc("Enable PPC64 register scavenger"), + cl::Hidden); +#define EnableRegisterScavenging \ + ((EnablePPC32RS && !Subtarget.isPPC64()) || \ + (EnablePPC64RS && Subtarget.isPPC64())) // FIXME (64-bit): Should be inlined. bool PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const { - return EnablePPCRS; + return EnableRegisterScavenging; } /// getRegisterNumbering - Given the enum value for some register, e.g. @@ -349,7 +356,7 @@ BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { Reserved.set(PPC::R13); Reserved.set(PPC::R31); - if (!EnablePPCRS) + if (!EnableRegisterScavenging) Reserved.set(PPC::R0); // FIXME (64-bit): Remove Reserved.set(PPC::X0); @@ -454,7 +461,7 @@ void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II, // FIXME (64-bit): Use "findScratchRegister" unsigned Reg; - if (EnablePPCRS) + if (EnableRegisterScavenging) Reg = findScratchRegister(II, RS, RC, SPAdj); else Reg = PPC::R0; @@ -464,7 +471,7 @@ void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II, .addReg(PPC::R31) .addImm(FrameSize); } else if (LP64) { - if (EnablePPCRS) // FIXME (64-bit): Use "true" version. + if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part. BuildMI(MBB, II, TII.get(PPC::LD), Reg) .addImm(0) .addReg(PPC::X1); @@ -481,7 +488,7 @@ void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II, // Grow the stack and update the stack pointer link, then determine the // address of new allocated space. if (LP64) { - if (EnablePPCRS) // FIXME (64-bit): Use "true" version. + if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part. BuildMI(MBB, II, TII.get(PPC::STDUX)) .addReg(Reg, false, false, true) .addReg(PPC::X1) @@ -616,7 +623,7 @@ void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, } // Special case for pseudo-op SPILL_CR. - if (EnablePPCRS) // FIXME (64-bit): Enable by default + if (EnableRegisterScavenging) // FIXME (64-bit): Enable by default. if (OpC == PPC::SPILL_CR) { lowerCRSpilling(II, FrameIndex, SPAdj, RS); return; @@ -670,7 +677,7 @@ void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, // FIXME (64-bit): Use "findScratchRegister". unsigned SReg; - if (EnablePPCRS) + if (EnableRegisterScavenging) SReg = findScratchRegister(II, RS, &PPC::GPRCRegClass, SPAdj); else SReg = PPC::R0; @@ -922,7 +929,7 @@ PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, // FIXME: doesn't detect whether or not we need to spill vXX, which requires // r0 for now. - if (EnablePPCRS) // FIXME (64-bit): Enable. + if (EnableRegisterScavenging) // FIXME (64-bit): Enable. if (needsFP(MF) || spillsCR(MF)) { const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; |