diff options
| author | Hal Finkel <hfinkel@anl.gov> | 2013-03-21 23:45:03 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2013-03-21 23:45:03 +0000 |
| commit | 7697370adff8983e2a3de493362f0d8c9f9b0e17 (patch) | |
| tree | 9879b047b1a9929ffc9b7fdef76b9389276c0791 /lib/Target/PowerPC/PPCRegisterInfo.cpp | |
| parent | 426db657da8753921f21c676b91c527e1b77878c (diff) | |
| download | llvm-7697370adff8983e2a3de493362f0d8c9f9b0e17.tar.gz llvm-7697370adff8983e2a3de493362f0d8c9f9b0e17.tar.bz2 llvm-7697370adff8983e2a3de493362f0d8c9f9b0e17.tar.xz | |
Remove the G8RC_NOX0_and_GPRC_NOR0 PPC register class
As Jakob pointed out in his review of r177423, having a shared ZERO
register between the 32- and 64-bit register classes causes this
odd G8RC_NOX0_and_GPRC_NOR0 class to be created. As recommended,
this adds a ZERO8 register which differentiates the 32- and 64-bit
zeros.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177683 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCRegisterInfo.cpp')
| -rw-r--r-- | lib/Target/PowerPC/PPCRegisterInfo.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index 150e241161..75e20e4a26 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -125,6 +125,7 @@ BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { // The ZERO register is not really a register, but the representation of r0 // when used in instructions that treat r0 as the constant 0. Reserved.set(PPC::ZERO); + Reserved.set(PPC::ZERO8); // The FP register is also not really a register, but is the representation // of the frame pointer register used by ISD::FRAMEADDR. |