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| author | Nicolas Geoffray <nicolas.geoffray@lip6.fr> | 2007-04-03 10:57:49 +0000 |
|---|---|---|
| committer | Nicolas Geoffray <nicolas.geoffray@lip6.fr> | 2007-04-03 10:57:49 +0000 |
| commit | cfcd8da70b33118ab3765ed54d63f497321932ce (patch) | |
| tree | f52735979331f4fe27da3dfe945e67bbd02ac332 /lib/Target/PowerPC/PPCRegisterInfo.cpp | |
| parent | ef3c030e0e08b7d9446445823f4972fcf18c1ce1 (diff) | |
| download | llvm-cfcd8da70b33118ab3765ed54d63f497321932ce.tar.gz llvm-cfcd8da70b33118ab3765ed54d63f497321932ce.tar.bz2 llvm-cfcd8da70b33118ab3765ed54d63f497321932ce.tar.xz | |
Addition to the previous commit for getCalleeSavedRegClasses:
"The ELF ABI specifies F1-F8 registers as argument registers for double, not
F1-F10. This affects only ELF, not MachO."
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35623 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCRegisterInfo.cpp')
| -rw-r--r-- | lib/Target/PowerPC/PPCRegisterInfo.cpp | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index 6bd2716011..095eab4217 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -378,7 +378,8 @@ PPCRegisterInfo::getCalleeSavedRegClasses() const { &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, - &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, + &PPC::F8RCRegClass, + &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, @@ -424,7 +425,8 @@ PPCRegisterInfo::getCalleeSavedRegClasses() const { &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, - &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, + &PPC::F8RCRegClass, + &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, |