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author | Nate Begeman <natebegeman@mac.com> | 2004-08-16 01:52:12 +0000 |
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committer | Nate Begeman <natebegeman@mac.com> | 2004-08-16 01:52:12 +0000 |
commit | 1cffdf0798eb2bb495bc234b27f9455dbb476d02 (patch) | |
tree | d76d41c671334ac801b0ffb29d4b937bec99094e /lib/Target/PowerPC/PPCRegisterInfo.td | |
parent | 865075ed350ec6cee8ccd6723362dc5aa3823b25 (diff) | |
download | llvm-1cffdf0798eb2bb495bc234b27f9455dbb476d02.tar.gz llvm-1cffdf0798eb2bb495bc234b27f9455dbb476d02.tar.bz2 llvm-1cffdf0798eb2bb495bc234b27f9455dbb476d02.tar.xz |
Fix frame pointer handling:
Reserve R0 in store/load from stack slot for building >32k offsets from SP
or FP. This also requires we use R11 rather than R0 for holding the LR
value we want to save or restore. Also, tell the register allocator not
to use R31 (our FP) in functions that have a frame pointer. These changes
fix Burg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15807 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCRegisterInfo.td')
-rw-r--r-- | lib/Target/PowerPC/PPCRegisterInfo.td | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.td b/lib/Target/PowerPC/PPCRegisterInfo.td index 6122bb57c7..ccd51b1b24 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.td +++ b/lib/Target/PowerPC/PPCRegisterInfo.td @@ -78,15 +78,18 @@ def TBU : SPR<5>; def GPRC : RegisterClass<i32, 4, [R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, - R31, R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17, - R16, R15, R14, R13, R0, R1, LR]> + R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17, + R16, R15, R14, R13, R31, R0, R1, LR]> { let Methods = [{ iterator allocation_order_begin(MachineFunction &MF) const { return begin() + (AIX ? 1 : 0); } iterator allocation_order_end(MachineFunction &MF) const { - return end() - 3; + if (hasFP(MF)) + return end()-4; + else + return end()-3; } }]; } |