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| author | Bill Schmidt <wschmidt@linux.vnet.ibm.com> | 2013-03-27 02:40:14 +0000 |
|---|---|---|
| committer | Bill Schmidt <wschmidt@linux.vnet.ibm.com> | 2013-03-27 02:40:14 +0000 |
| commit | 37ef805818e32531c2c3a454fee33f06f363f9c2 (patch) | |
| tree | b6345c208b28f4af25e6f6b5bf47b903916cbf5a /lib/Target/PowerPC/PPCRegisterInfo.td | |
| parent | d841d6f71e4e95087a2eb509cedb50f7b5bfe142 (diff) | |
| download | llvm-37ef805818e32531c2c3a454fee33f06f363f9c2.tar.gz llvm-37ef805818e32531c2c3a454fee33f06f363f9c2.tar.bz2 llvm-37ef805818e32531c2c3a454fee33f06f363f9c2.tar.xz | |
Remove the link register from the GPR classes on PowerPC.
Some implementation detail in the forgotten past required the link
register to be placed in the GPRC and G8RC register classes. This is
just wrong on the face of it, and causes several extra intersection
register classes to be generated. I found this was having evil
effects on instruction scheduling, by causing the wrong register class
to be consulted for register pressure decisions.
No code generation changes are expected, other than some minor changes
in instruction order. Seven tests in the test bucket required minor
tweaks to adjust to the new normal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178114 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCRegisterInfo.td')
| -rw-r--r-- | lib/Target/PowerPC/PPCRegisterInfo.td | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.td b/lib/Target/PowerPC/PPCRegisterInfo.td index c5e325545d..aa5584ee3c 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.td +++ b/lib/Target/PowerPC/PPCRegisterInfo.td @@ -172,11 +172,11 @@ def RM: SPR<512, "**ROUNDING MODE**">; // then nonvolatiles in reverse order since stmw/lmw save from rN to r31 def GPRC : RegisterClass<"PPC", [i32], 32, (add (sequence "R%u", 2, 12), (sequence "R%u", 30, 13), - R31, R0, R1, LR, FP)>; + R31, R0, R1, FP)>; def G8RC : RegisterClass<"PPC", [i64], 64, (add (sequence "X%u", 2, 12), (sequence "X%u", 30, 14), - X31, X13, X0, X1, LR8, FP8)>; + X31, X13, X0, X1, FP8)>; // For some instructions r0 is special (representing the value 0 instead of // the value in the r0 register), and we use these register subclasses to |