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| author | Hal Finkel <hfinkel@anl.gov> | 2014-03-26 16:12:58 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2014-03-26 16:12:58 +0000 |
| commit | 7363d2223e09fd78094fba652223785f0d63c196 (patch) | |
| tree | 832288b11dc53f379298b32c7aef71cfed503783 /lib/Target/PowerPC/PPCRegisterInfo.td | |
| parent | 8e7aa4be58277562240e5083a18bd52d6e76abf5 (diff) | |
| download | llvm-7363d2223e09fd78094fba652223785f0d63c196.tar.gz llvm-7363d2223e09fd78094fba652223785f0d63c196.tar.bz2 llvm-7363d2223e09fd78094fba652223785f0d63c196.tar.xz | |
[PowerPC] Add v2i64 as a legal VSX type
v2i64 needs to be a legal VSX type because it is the SetCC result type from
v2f64 comparisons. We need to expand all non-arithmetic v2i64 operations.
This fixes the lowering for v2f64 VSELECT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204828 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCRegisterInfo.td')
| -rw-r--r-- | lib/Target/PowerPC/PPCRegisterInfo.td | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.td b/lib/Target/PowerPC/PPCRegisterInfo.td index 339d4e4d71..dab222b7bb 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.td +++ b/lib/Target/PowerPC/PPCRegisterInfo.td @@ -235,16 +235,16 @@ def VRRC : RegisterClass<"PPC", [v16i8,v8i16,v4i32,v4f32], 128, // VSX register classes (the allocation order mirrors that of the corresponding // subregister classes). -def VSLRC : RegisterClass<"PPC", [v4i32,v4f32,f64,v2f64], 128, +def VSLRC : RegisterClass<"PPC", [v4i32,v4f32,f64,v2f64,v2i64], 128, (add (sequence "VSL%u", 0, 13), (sequence "VSL%u", 31, 14))>; -def VSHRC : RegisterClass<"PPC", [v4i32,v4f32,f64,v2f64], 128, +def VSHRC : RegisterClass<"PPC", [v4i32,v4f32,f64,v2f64,v2i64], 128, (add VSH2, VSH3, VSH4, VSH5, VSH0, VSH1, VSH6, VSH7, VSH8, VSH9, VSH10, VSH11, VSH12, VSH13, VSH14, VSH15, VSH16, VSH17, VSH18, VSH19, VSH31, VSH30, VSH29, VSH28, VSH27, VSH26, VSH25, VSH24, VSH23, VSH22, VSH21, VSH20)>; -def VSRC : RegisterClass<"PPC", [v4i32,v4f32,f64,v2f64], 128, +def VSRC : RegisterClass<"PPC", [v4i32,v4f32,f64,v2f64,v2i64], 128, (add VSLRC, VSHRC)>; def CRBITRC : RegisterClass<"PPC", [i1], 32, |