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| author | Hal Finkel <hfinkel@anl.gov> | 2013-03-21 23:45:03 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2013-03-21 23:45:03 +0000 |
| commit | 7697370adff8983e2a3de493362f0d8c9f9b0e17 (patch) | |
| tree | 9879b047b1a9929ffc9b7fdef76b9389276c0791 /lib/Target/PowerPC/PPCRegisterInfo.td | |
| parent | 426db657da8753921f21c676b91c527e1b77878c (diff) | |
| download | llvm-7697370adff8983e2a3de493362f0d8c9f9b0e17.tar.gz llvm-7697370adff8983e2a3de493362f0d8c9f9b0e17.tar.bz2 llvm-7697370adff8983e2a3de493362f0d8c9f9b0e17.tar.xz | |
Remove the G8RC_NOX0_and_GPRC_NOR0 PPC register class
As Jakob pointed out in his review of r177423, having a shared ZERO
register between the 32- and 64-bit register classes causes this
odd G8RC_NOX0_and_GPRC_NOR0 class to be created. As recommended,
this adds a ZERO8 register which differentiates the 32- and 64-bit
zeros.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177683 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCRegisterInfo.td')
| -rw-r--r-- | lib/Target/PowerPC/PPCRegisterInfo.td | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.td b/lib/Target/PowerPC/PPCRegisterInfo.td index e91bf7fe5d..55d36bbfc9 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.td +++ b/lib/Target/PowerPC/PPCRegisterInfo.td @@ -87,7 +87,8 @@ foreach Index = 0-31 in { } // The reprsentation of r0 when treated as the constant 0. -def ZERO : GPR<0, "r0">; +def ZERO : GPR<0, "r0">; +def ZERO8 : GP8<ZERO, "r0">; // Representations of the frame pointer used by ISD::FRAMEADDR. def FP : GPR<0 /* arbitrary */, "**FRAME POINTER**">; @@ -181,7 +182,7 @@ def G8RC : RegisterClass<"PPC", [i64], 64, (add (sequence "X%u", 2, 12), // the value in the r0 register), and we use these register subclasses to // prevent r0 from being allocated for use by those instructions. def GPRC_NOR0 : RegisterClass<"PPC", [i32], 32, (add (sub GPRC, R0), ZERO)>; -def G8RC_NOX0 : RegisterClass<"PPC", [i64], 64, (add (sub G8RC, X0), ZERO)>; +def G8RC_NOX0 : RegisterClass<"PPC", [i64], 64, (add (sub G8RC, X0), ZERO8)>; // Allocate volatiles first, then non-volatiles in reverse order. With the SVR4 // ABI the size of the Floating-point register save area is determined by the |