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| author | Misha Brukman <brukman+llvm@gmail.com> | 2004-08-11 23:44:55 +0000 |
|---|---|---|
| committer | Misha Brukman <brukman+llvm@gmail.com> | 2004-08-11 23:44:55 +0000 |
| commit | dceb4576075546962ac816a05267afbc606234a6 (patch) | |
| tree | e10939cb7813b91021e86a7d1b7a3c18015868ee /lib/Target/PowerPC/PPCRegisterInfo.td | |
| parent | ca9309f22e626db9019de371cf7b61a7e35d08e2 (diff) | |
| download | llvm-dceb4576075546962ac816a05267afbc606234a6.tar.gz llvm-dceb4576075546962ac816a05267afbc606234a6.tar.bz2 llvm-dceb4576075546962ac816a05267afbc606234a6.tar.xz | |
* Set the is64bit boolean flag in PowerPCRegisterInfo
* Doubles are 8 bytes in 64-bit PowerPC, and use the general register class
* Use double-word loads and stores for restoring from/saving to stack
* Do not allocate R2 if compiling for AIX
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15670 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCRegisterInfo.td')
| -rw-r--r-- | lib/Target/PowerPC/PPCRegisterInfo.td | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.td b/lib/Target/PowerPC/PPCRegisterInfo.td index 34ebfac610..c103dd6f37 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.td +++ b/lib/Target/PowerPC/PPCRegisterInfo.td @@ -77,13 +77,13 @@ def TBU : SPR<5>; // then nonvolatiles in reverse order since stmw/lmw save from rN to r31 def GPRC : RegisterClass<i32, 4, - [R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, + [R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R31, R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17, - R16, R15, R14, R13, R0, R1, LR]> + R16, R15, R14, R13, R0, R2, R1, LR]> { let Methods = [{ iterator allocation_order_end(MachineFunction &MF) const { - return end()-3; + return end() - (AIX ? 4 : 3); } }]; } |