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| author | Hal Finkel <hfinkel@anl.gov> | 2012-06-12 19:01:24 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2012-06-12 19:01:24 +0000 |
| commit | 16803097fbefa313fdadc3adede659bd0e52cec1 (patch) | |
| tree | adae514a243b76a64b371118ff635c54f340a934 /lib/Target/PowerPC/PPCSchedule440.td | |
| parent | b9c592f4c554888c095863cf1e7cda350a371b6c (diff) | |
| download | llvm-16803097fbefa313fdadc3adede659bd0e52cec1.tar.gz llvm-16803097fbefa313fdadc3adede659bd0e52cec1.tar.bz2 llvm-16803097fbefa313fdadc3adede659bd0e52cec1.tar.xz | |
Split out the PPC instruction class IntSimple from IntGeneral.
On the POWER7, adds and logical operations can also be handled
in the load/store pipelines. We'll call these IntSimple.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158366 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCSchedule440.td')
| -rw-r--r-- | lib/Target/PowerPC/PPCSchedule440.td | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/lib/Target/PowerPC/PPCSchedule440.td b/lib/Target/PowerPC/PPCSchedule440.td index 9921fc8b95..cd0fb70a24 100644 --- a/lib/Target/PowerPC/PPCSchedule440.td +++ b/lib/Target/PowerPC/PPCSchedule440.td @@ -108,6 +108,15 @@ def PPC440Itineraries : ProcessorItineraries< IRACC, IEXE1, IEXE2, IWB, LRACC, JEXE1, JEXE2, JWB, AGEN, CRD, LWB, FEXE1, FEXE2, FEXE3, FEXE4, FEXE5, FEXE6, FWB, LWARX_Hold], [GPR_Bypass, FPR_Bypass], [ + InstrItinData<IntSimple , [InstrStage<1, [IFTH1, IFTH2]>, + InstrStage<1, [PDCD1, PDCD2]>, + InstrStage<1, [DISS1, DISS2]>, + InstrStage<1, [IRACC, LRACC]>, + InstrStage<1, [IEXE1, JEXE1]>, + InstrStage<1, [IEXE2, JEXE2]>, + InstrStage<1, [IWB, JWB]>], + [6, 4, 4], + [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, InstrItinData<IntGeneral , [InstrStage<1, [IFTH1, IFTH2]>, InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [DISS1, DISS2]>, |