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| author | Jim Laskey <jlaskey@mac.com> | 2005-10-19 19:51:16 +0000 |
|---|---|---|
| committer | Jim Laskey <jlaskey@mac.com> | 2005-10-19 19:51:16 +0000 |
| commit | 538421411a4a0a070bbd789e88657689ca504dbe (patch) | |
| tree | e82291119677cb6e787ec7acf45238d06297cc47 /lib/Target/PowerPC/PPCScheduleG4.td | |
| parent | 3d925442619eabbca9ac7d0ac2e25ee79c01c31c (diff) | |
| download | llvm-538421411a4a0a070bbd789e88657689ca504dbe.tar.gz llvm-538421411a4a0a070bbd789e88657689ca504dbe.tar.bz2 llvm-538421411a4a0a070bbd789e88657689ca504dbe.tar.xz | |
Added InstrSchedClass to each of the PowerPC Instructions.
Note that when adding new instructions that you should refer to the table at the
bottom of PPCSchedule.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23830 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCScheduleG4.td')
| -rw-r--r-- | lib/Target/PowerPC/PPCScheduleG4.td | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/PowerPC/PPCScheduleG4.td b/lib/Target/PowerPC/PPCScheduleG4.td index 2b1818a24f..d0e445605f 100644 --- a/lib/Target/PowerPC/PPCScheduleG4.td +++ b/lib/Target/PowerPC/PPCScheduleG4.td @@ -30,15 +30,15 @@ def G4Itineraries : ProcessorItineraries<[ InstrItinData<BrMCRX , [InstrStage<1, [SRU]>]>, InstrItinData<LdStDCBF , [InstrStage<2, [SLU]>]>, InstrItinData<LdStDCBI , [InstrStage<2, [SLU]>]>, - InstrItinData<LdStDCBT , [InstrStage<2, [SLU]>]>, + InstrItinData<LdStGeneral , [InstrStage<2, [SLU]>]>, InstrItinData<LdStDSS , [InstrStage<2, [SLU]>]>, InstrItinData<LdStICBI , [InstrStage<2, [SLU]>]>, - InstrItinData<LdStLBZUX , [InstrStage<2, [SLU]>]>, + InstrItinData<LdStUX , [InstrStage<2, [SLU]>]>, InstrItinData<LdStLFD , [InstrStage<2, [SLU]>]>, InstrItinData<LdStLFDU , [InstrStage<2, [SLU]>]>, InstrItinData<LdStLHA , [InstrStage<2, [SLU]>]>, InstrItinData<LdStLMW , [InstrStage<34, [SLU]>]>, - InstrItinData<LdStLVEBX , [InstrStage<2, [SLU]>]>, + InstrItinData<LdStLVecX , [InstrStage<2, [SLU]>]>, InstrItinData<LdStLWARX , [InstrStage<3, [SLU]>]>, InstrItinData<LdStSTVEBX , [InstrStage<2, [SLU]>]>, InstrItinData<LdStSTWCX , [InstrStage<5, [SLU]>]>, |