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| author | Hal Finkel <hfinkel@anl.gov> | 2013-11-30 20:41:13 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2013-11-30 20:41:13 +0000 |
| commit | bc0bdb26da10037e182d83707aeb51b49ae35d8a (patch) | |
| tree | 265e2fed2c383433b456d57a11a2fd8348d39359 /lib/Target/PowerPC/PPCScheduleG5.td | |
| parent | 6e1de2e63ee831e01b6e7eaa123e1e0e270bac76 (diff) | |
| download | llvm-bc0bdb26da10037e182d83707aeb51b49ae35d8a.tar.gz llvm-bc0bdb26da10037e182d83707aeb51b49ae35d8a.tar.bz2 llvm-bc0bdb26da10037e182d83707aeb51b49ae35d8a.tar.xz | |
Split some PPC itinerary classes
In preparation for adding scheduling definitions for the POWER7, split some PPC
itinerary classes so that the P7's latencies and hazards can be better
described. For the most part, this means differentiating indexed from non-index
pre-increment loads and stores. Also, differentiate single from
double-precision sqrt.
No functionality change intended (except for a more-specific latency for
single-precision sqrt on the A2).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195980 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCScheduleG5.td')
| -rw-r--r-- | lib/Target/PowerPC/PPCScheduleG5.td | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/lib/Target/PowerPC/PPCScheduleG5.td b/lib/Target/PowerPC/PPCScheduleG5.td index 2329e58b1c..a3b73ab445 100644 --- a/lib/Target/PowerPC/PPCScheduleG5.td +++ b/lib/Target/PowerPC/PPCScheduleG5.td @@ -52,6 +52,7 @@ def G5Itineraries : ProcessorItineraries< InstrItinData<IIC_LdStDCBF , [InstrStage<3, [G5_SLU]>]>, InstrItinData<IIC_LdStLoad , [InstrStage<3, [G5_SLU]>]>, InstrItinData<IIC_LdStLoadUpd , [InstrStage<3, [G5_SLU]>]>, + InstrItinData<IIC_LdStLoadUpdX, [InstrStage<3, [G5_SLU]>]>, InstrItinData<IIC_LdStStore , [InstrStage<3, [G5_SLU]>]>, InstrItinData<IIC_LdStStoreUpd, [InstrStage<3, [G5_SLU]>]>, InstrItinData<IIC_LdStDSS , [InstrStage<10, [G5_SLU]>]>, @@ -60,11 +61,14 @@ def G5Itineraries : ProcessorItineraries< InstrItinData<IIC_LdStSTFDU , [InstrStage<4, [G5_SLU]>]>, InstrItinData<IIC_LdStLD , [InstrStage<3, [G5_SLU]>]>, InstrItinData<IIC_LdStLDU , [InstrStage<3, [G5_SLU]>]>, + InstrItinData<IIC_LdStLDUX , [InstrStage<3, [G5_SLU]>]>, InstrItinData<IIC_LdStLDARX , [InstrStage<11, [G5_SLU]>]>, InstrItinData<IIC_LdStLFD , [InstrStage<3, [G5_SLU]>]>, InstrItinData<IIC_LdStLFDU , [InstrStage<5, [G5_SLU]>]>, + InstrItinData<IIC_LdStLFDUX , [InstrStage<5, [G5_SLU]>]>, InstrItinData<IIC_LdStLHA , [InstrStage<5, [G5_SLU]>]>, InstrItinData<IIC_LdStLHAU , [InstrStage<5, [G5_SLU]>]>, + InstrItinData<IIC_LdStLHAUX , [InstrStage<5, [G5_SLU]>]>, InstrItinData<IIC_LdStLMW , [InstrStage<64, [G5_SLU]>]>, InstrItinData<IIC_LdStLVecX , [InstrStage<3, [G5_SLU]>]>, InstrItinData<IIC_LdStLWA , [InstrStage<5, [G5_SLU]>]>, @@ -73,6 +77,7 @@ def G5Itineraries : ProcessorItineraries< InstrItinData<IIC_LdStSLBIE , [InstrStage<2, [G5_SLU]>]>, InstrItinData<IIC_LdStSTD , [InstrStage<3, [G5_SLU]>]>, InstrItinData<IIC_LdStSTDU , [InstrStage<3, [G5_SLU]>]>, + InstrItinData<IIC_LdStSTDUX , [InstrStage<3, [G5_SLU]>]>, InstrItinData<IIC_LdStSTDCX , [InstrStage<11, [G5_SLU]>]>, InstrItinData<IIC_LdStSTVEBX , [InstrStage<5, [G5_SLU]>]>, InstrItinData<IIC_LdStSTWCX , [InstrStage<11, [G5_SLU]>]>, @@ -83,6 +88,7 @@ def G5Itineraries : ProcessorItineraries< InstrItinData<IIC_SprMTSR , [InstrStage<3, [G5_SLU]>]>, InstrItinData<IIC_SprTLBSYNC , [InstrStage<3, [G5_SLU]>]>, InstrItinData<IIC_SprMFCR , [InstrStage<2, [G5_IU2]>]>, + InstrItinData<IIC_SprMFCRF , [InstrStage<2, [G5_IU2]>]>, InstrItinData<IIC_SprMFMSR , [InstrStage<3, [G5_IU2]>]>, InstrItinData<IIC_SprMFSPR , [InstrStage<3, [G5_IU2]>]>, InstrItinData<IIC_SprMFTB , [InstrStage<10, [G5_IU2]>]>, @@ -95,7 +101,8 @@ def G5Itineraries : ProcessorItineraries< InstrItinData<IIC_FPDivS , [InstrStage<33, [G5_FPU1, G5_FPU2]>]>, InstrItinData<IIC_FPFused , [InstrStage<6, [G5_FPU1, G5_FPU2]>]>, InstrItinData<IIC_FPRes , [InstrStage<6, [G5_FPU1, G5_FPU2]>]>, - InstrItinData<IIC_FPSqrt , [InstrStage<40, [G5_FPU1, G5_FPU2]>]>, + InstrItinData<IIC_FPSqrtD , [InstrStage<40, [G5_FPU1, G5_FPU2]>]>, + InstrItinData<IIC_FPSqrtS , [InstrStage<40, [G5_FPU1, G5_FPU2]>]>, InstrItinData<IIC_VecGeneral , [InstrStage<2, [G5_VIU1]>]>, InstrItinData<IIC_VecFP , [InstrStage<8, [G5_VFPU]>]>, InstrItinData<IIC_VecFPCompare, [InstrStage<2, [G5_VFPU]>]>, |