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authorHal Finkel <hfinkel@anl.gov>2012-04-01 19:22:40 +0000
committerHal Finkel <hfinkel@anl.gov>2012-04-01 19:22:40 +0000
commit4d989ac93ce608057fb6b13a4068264ab037ecd5 (patch)
tree2dad7e6b65936307c353e73de55e3b9187d4cb26 /lib/Target/PowerPC/PPCSubtarget.cpp
parent413b2e7539a1e41f8694abb809678ae48d1e6125 (diff)
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Add instruction itinerary for the PPC64 A2 core.
This adds a full itinerary for IBM's PPC64 A2 embedded core. These cores form the basis for the CPUs in the new IBM BG/Q supercomputer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153842 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCSubtarget.cpp')
-rw-r--r--lib/Target/PowerPC/PPCSubtarget.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/PowerPC/PPCSubtarget.cpp b/lib/Target/PowerPC/PPCSubtarget.cpp
index c89fab3356..fa54a44029 100644
--- a/lib/Target/PowerPC/PPCSubtarget.cpp
+++ b/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -146,7 +146,7 @@ bool PPCSubtarget::enablePostRAScheduler(
CodeGenOpt::Level OptLevel,
TargetSubtargetInfo::AntiDepBreakMode& Mode,
RegClassVector& CriticalPathRCs) const {
- if (DarwinDirective == PPC::DIR_440)
+ if (DarwinDirective == PPC::DIR_440 || DarwinDirective == PPC::DIR_A2)
return false;
Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;