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author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-06-23 18:00:44 +0000 |
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committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-06-23 18:00:44 +0000 |
commit | 5f607c0b392efa72d3dcb6486a2f164528f48ebe (patch) | |
tree | fcbd951e34de3931d3de54e39039f0294b04405f /lib/Target/R600/AMDGPUISelLowering.cpp | |
parent | a12b356464afd0d22950ce9c7025fd7fc4fcedf2 (diff) | |
download | llvm-5f607c0b392efa72d3dcb6486a2f164528f48ebe.tar.gz llvm-5f607c0b392efa72d3dcb6486a2f164528f48ebe.tar.bz2 llvm-5f607c0b392efa72d3dcb6486a2f164528f48ebe.tar.xz |
R600: Move more out of AMDILISelLowering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211516 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/AMDGPUISelLowering.cpp')
-rw-r--r-- | lib/Target/R600/AMDGPUISelLowering.cpp | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/lib/Target/R600/AMDGPUISelLowering.cpp b/lib/Target/R600/AMDGPUISelLowering.cpp index f2cda63e90..87c396dd50 100644 --- a/lib/Target/R600/AMDGPUISelLowering.cpp +++ b/lib/Target/R600/AMDGPUISelLowering.cpp @@ -111,6 +111,14 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) : // Initialize target lowering borrowed from AMDIL InitAMDILLowering(); + setOperationAction(ISD::Constant, MVT::i32, Legal); + setOperationAction(ISD::Constant, MVT::i64, Legal); + setOperationAction(ISD::ConstantFP, MVT::f32, Legal); + setOperationAction(ISD::ConstantFP, MVT::f64, Legal); + + setOperationAction(ISD::BR_JT, MVT::Other, Expand); + setOperationAction(ISD::BRIND, MVT::Other, Expand); + // We need to custom lower some of the intrinsics setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); @@ -300,6 +308,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) : setOperationAction(ISD::UDIVREM, VT, Custom); setOperationAction(ISD::SELECT, VT, Expand); setOperationAction(ISD::VSELECT, VT, Expand); + setOperationAction(ISD::SELECT_CC, VT, Expand); setOperationAction(ISD::XOR, VT, Expand); setOperationAction(ISD::BSWAP, VT, Expand); setOperationAction(ISD::CTPOP, VT, Expand); @@ -307,6 +316,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) : setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand); setOperationAction(ISD::CTLZ, VT, Expand); setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand); + setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand); } static const MVT::SimpleValueType FloatVectorTypes[] = { @@ -333,7 +343,9 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) : setOperationAction(ISD::FNEG, VT, Expand); setOperationAction(ISD::SELECT, VT, Expand); setOperationAction(ISD::VSELECT, VT, Expand); + setOperationAction(ISD::SELECT_CC, VT, Expand); setOperationAction(ISD::FCOPYSIGN, VT, Expand); + setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand); } setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom); @@ -348,6 +360,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) : // There are no integer divide instructions, and these expand to a pretty // large sequence of instructions. setIntDivIsCheap(false); + setPow2DivIsCheap(false); // TODO: Investigate this when 64-bit divides are implemented. addBypassSlowDiv(64, 32); |