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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-11-13 23:36:50 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-11-13 23:36:50 +0000 |
| commit | a2b4eb6d15a13de257319ac6231b5ab622cd02b1 (patch) | |
| tree | 3147a7994db9c80cbaa22526fae0dbfdc780c212 /lib/Target/R600/AMDGPUInstructions.td | |
| parent | b52bf6a3b31596a309f4b12884522e9b4a344654 (diff) | |
| download | llvm-a2b4eb6d15a13de257319ac6231b5ab622cd02b1.tar.gz llvm-a2b4eb6d15a13de257319ac6231b5ab622cd02b1.tar.bz2 llvm-a2b4eb6d15a13de257319ac6231b5ab622cd02b1.tar.xz | |
R600/SI: Add support for private address space load/store
Private address space is emulated using the register file with
MOVRELS and MOVRELD instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194626 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/AMDGPUInstructions.td')
| -rw-r--r-- | lib/Target/R600/AMDGPUInstructions.td | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/lib/Target/R600/AMDGPUInstructions.td b/lib/Target/R600/AMDGPUInstructions.td index 0c81a6b0a6..3e1fc27e12 100644 --- a/lib/Target/R600/AMDGPUInstructions.td +++ b/lib/Target/R600/AMDGPUInstructions.td @@ -35,6 +35,7 @@ class AMDGPUShaderInst <dag outs, dag ins, string asm, list<dag> pattern> } def InstFlag : OperandWithDefaultOps <i32, (ops (i32 0))>; +def ADDRIndirect : ComplexPattern<iPTR, 2, "SelectADDRIndirect", [], []>; def COND_EQ : PatLeaf < (cond), @@ -277,6 +278,8 @@ class FNEG <RegisterClass rc> : AMDGPUShaderInst < multiclass RegisterLoadStore <RegisterClass dstClass, Operand addrClass, ComplexPattern addrPat> { +let UseNamedOperandTable = 1 in { + def RegisterLoad : AMDGPUShaderInst < (outs dstClass:$dst), (ins addrClass:$addr, i32imm:$chan), @@ -295,6 +298,7 @@ multiclass RegisterLoadStore <RegisterClass dstClass, Operand addrClass, let isRegisterStore = 1; } } +} } // End isCodeGenOnly = 1, isPseudo = 1 |