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author | Tom Stellard <thomas.stellard@amd.com> | 2014-05-16 20:56:47 +0000 |
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committer | Tom Stellard <thomas.stellard@amd.com> | 2014-05-16 20:56:47 +0000 |
commit | 17200e3bb3ae6c677f5d53aad13c0fbd761cfda7 (patch) | |
tree | 2536466e9bd2fd68020d1929b66b8c7b2c70383e /lib/Target/R600/AMDGPUMCInstLower.cpp | |
parent | 9d99d7a1854b9aa00091f6588664512a6213fc77 (diff) | |
download | llvm-17200e3bb3ae6c677f5d53aad13c0fbd761cfda7.tar.gz llvm-17200e3bb3ae6c677f5d53aad13c0fbd761cfda7.tar.bz2 llvm-17200e3bb3ae6c677f5d53aad13c0fbd761cfda7.tar.xz |
R600/SI: Refactor the VOP3_32 tablegen class
This will allow us to use a single MachineInstr to represent
instructions which behave the same but have different encodings
on some subtargets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209028 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/AMDGPUMCInstLower.cpp')
-rw-r--r-- | lib/Target/R600/AMDGPUMCInstLower.cpp | 28 |
1 files changed, 24 insertions, 4 deletions
diff --git a/lib/Target/R600/AMDGPUMCInstLower.cpp b/lib/Target/R600/AMDGPUMCInstLower.cpp index d65b00f018..66d1074321 100644 --- a/lib/Target/R600/AMDGPUMCInstLower.cpp +++ b/lib/Target/R600/AMDGPUMCInstLower.cpp @@ -17,6 +17,7 @@ #include "AMDGPUAsmPrinter.h" #include "InstPrinter/AMDGPUInstPrinter.h" #include "R600InstrInfo.h" +#include "SIInstrInfo.h" #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/IR/Constants.h" @@ -31,12 +32,30 @@ using namespace llvm; -AMDGPUMCInstLower::AMDGPUMCInstLower(MCContext &ctx): - Ctx(ctx) +AMDGPUMCInstLower::AMDGPUMCInstLower(MCContext &ctx, const AMDGPUSubtarget &st): + Ctx(ctx), ST(st) { } +enum AMDGPUMCInstLower::SISubtarget +AMDGPUMCInstLower::AMDGPUSubtargetToSISubtarget(unsigned Gen) const { + switch (Gen) { + default: return AMDGPUMCInstLower::SI; + } +} + +unsigned AMDGPUMCInstLower::getMCOpcode(unsigned MIOpcode) const { + + int MCOpcode = AMDGPU::getMCOpcode(MIOpcode, + AMDGPUSubtargetToSISubtarget(ST.getGeneration())); + if (MCOpcode == -1) + MCOpcode = MIOpcode; + + return MCOpcode; +} + void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const { - OutMI.setOpcode(MI->getOpcode()); + + OutMI.setOpcode(getMCOpcode(MI->getOpcode())); for (const MachineOperand &MO : MI->explicit_operands()) { MCOperand MCOp; @@ -65,7 +84,8 @@ void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const { } void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) { - AMDGPUMCInstLower MCInstLowering(OutContext); + AMDGPUMCInstLower MCInstLowering(OutContext, + MF->getTarget().getSubtarget<AMDGPUSubtarget>()); #ifdef _DEBUG StringRef Err; |