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author | Tom Stellard <thomas.stellard@amd.com> | 2014-05-16 20:56:47 +0000 |
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committer | Tom Stellard <thomas.stellard@amd.com> | 2014-05-16 20:56:47 +0000 |
commit | 17200e3bb3ae6c677f5d53aad13c0fbd761cfda7 (patch) | |
tree | 2536466e9bd2fd68020d1929b66b8c7b2c70383e /lib/Target/R600/AMDGPUMCInstLower.h | |
parent | 9d99d7a1854b9aa00091f6588664512a6213fc77 (diff) | |
download | llvm-17200e3bb3ae6c677f5d53aad13c0fbd761cfda7.tar.gz llvm-17200e3bb3ae6c677f5d53aad13c0fbd761cfda7.tar.bz2 llvm-17200e3bb3ae6c677f5d53aad13c0fbd761cfda7.tar.xz |
R600/SI: Refactor the VOP3_32 tablegen class
This will allow us to use a single MachineInstr to represent
instructions which behave the same but have different encodings
on some subtargets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209028 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/AMDGPUMCInstLower.h')
-rw-r--r-- | lib/Target/R600/AMDGPUMCInstLower.h | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/lib/Target/R600/AMDGPUMCInstLower.h b/lib/Target/R600/AMDGPUMCInstLower.h index d7d538e925..2b7f1e3074 100644 --- a/lib/Target/R600/AMDGPUMCInstLower.h +++ b/lib/Target/R600/AMDGPUMCInstLower.h @@ -13,16 +13,30 @@ namespace llvm { +class AMDGPUSubtarget; class MCInst; class MCContext; class MachineInstr; class AMDGPUMCInstLower { + // This must be kept in sync with the SISubtarget class in SIInstrInfo.td + enum SISubtarget { + SI = 0 + }; + MCContext &Ctx; + const AMDGPUSubtarget &ST; + + /// Convert a member of the AMDGPUSubtarget::Generation enum to the + /// SISubtarget enum. + enum SISubtarget AMDGPUSubtargetToSISubtarget(unsigned Gen) const; + + /// Get the MC opcode for this MachineInstr. + unsigned getMCOpcode(unsigned MIOpcode) const; public: - AMDGPUMCInstLower(MCContext &ctx); + AMDGPUMCInstLower(MCContext &ctx, const AMDGPUSubtarget &ST); /// \brief Lower a MachineInstr to an MCInst void lower(const MachineInstr *MI, MCInst &OutMI) const; |