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| author | Tom Stellard <thomas.stellard@amd.com> | 2014-04-07 19:45:41 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2014-04-07 19:45:41 +0000 |
| commit | 5c9bb7119a54f71b8b04e113c3e357e35bf065d8 (patch) | |
| tree | 4b3b90b5e290b08da886c46fb8ec65b020122a07 /lib/Target/R600/CaymanInstructions.td | |
| parent | dd2d4303527c4be7d5a050f1cc11831e76114181 (diff) | |
| download | llvm-5c9bb7119a54f71b8b04e113c3e357e35bf065d8.tar.gz llvm-5c9bb7119a54f71b8b04e113c3e357e35bf065d8.tar.bz2 llvm-5c9bb7119a54f71b8b04e113c3e357e35bf065d8.tar.xz | |
R600: Match 24-bit arithmetic patterns in a Target DAGCombine
Moving these patterns from TableGen files to PerformDAGCombine()
should allow us to generate better code by eliminating unnecessary
shifts and extensions earlier.
This also fixes a bug where the MAD pattern was calling
SimplifyDemandedBits with a 24-bit mask on the first operand
even when the full pattern wasn't being matched. This occasionally
resulted in some instructions being incorrectly deleted from the
program.
v2:
- Fix bug with 64-bit mul
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205731 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/CaymanInstructions.td')
| -rw-r--r-- | lib/Target/R600/CaymanInstructions.td | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/R600/CaymanInstructions.td b/lib/Target/R600/CaymanInstructions.td index acd7bdecdc..837d602533 100644 --- a/lib/Target/R600/CaymanInstructions.td +++ b/lib/Target/R600/CaymanInstructions.td @@ -21,10 +21,10 @@ def isCayman : Predicate<"Subtarget.hasCaymanISA()">; let Predicates = [isCayman] in { def MULADD_INT24_cm : R600_3OP <0x08, "MULADD_INT24", - [(set i32:$dst, (add (mul I24:$src0, I24:$src1), i32:$src2))], VecALU + [(set i32:$dst, (add (AMDGPUmul_i24 i32:$src0, i32:$src1), i32:$src2))], VecALU >; def MUL_INT24_cm : R600_2OP <0x5B, "MUL_INT24", - [(set i32:$dst, (mul I24:$src0, I24:$src1))], VecALU + [(set i32:$dst, (AMDGPUmul_i24 i32:$src0, i32:$src1))], VecALU >; let isVector = 1 in { |