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author | David Woodhouse <dwmw2@infradead.org> | 2014-01-28 23:13:07 +0000 |
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committer | David Woodhouse <dwmw2@infradead.org> | 2014-01-28 23:13:07 +0000 |
commit | 2ddea4b44d7d0f8b016d49bd8a16146f84a2a27e (patch) | |
tree | a8e2291865f7ee75b392a8ce5aa085e5f54f0056 /lib/Target/R600/MCTargetDesc | |
parent | 41c8ba9d61acb86847ad6cf823656e212d8dbbf5 (diff) | |
download | llvm-2ddea4b44d7d0f8b016d49bd8a16146f84a2a27e.tar.gz llvm-2ddea4b44d7d0f8b016d49bd8a16146f84a2a27e.tar.bz2 llvm-2ddea4b44d7d0f8b016d49bd8a16146f84a2a27e.tar.xz |
Explictly pass MCSubtargetInfo to MCCodeEmitter::EncodeInstruction()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200348 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/MCTargetDesc')
-rw-r--r-- | lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp | 6 | ||||
-rw-r--r-- | lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp | 6 |
2 files changed, 8 insertions, 4 deletions
diff --git a/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp b/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp index dd8df65d66..24609bb24d 100644 --- a/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp +++ b/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp @@ -44,7 +44,8 @@ public: /// \brief Encode the instruction and write it to the OS. virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS, - SmallVectorImpl<MCFixup> &Fixups) const; + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const; /// \returns the encoding for an MCOperand. virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, @@ -87,7 +88,8 @@ MCCodeEmitter *llvm::createR600MCCodeEmitter(const MCInstrInfo &MCII, } void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS, - SmallVectorImpl<MCFixup> &Fixups) const { + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const { const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); if (MI.getOpcode() == AMDGPU::RETURN || MI.getOpcode() == AMDGPU::FETCH_CLAUSE || diff --git a/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp b/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp index fc4ed35c18..53dad5a08c 100644 --- a/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp +++ b/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp @@ -55,7 +55,8 @@ public: /// \brief Encode the instruction and write it to the OS. virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS, - SmallVectorImpl<MCFixup> &Fixups) const; + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const; /// \returns the encoding for an MCOperand. virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, @@ -125,7 +126,8 @@ uint32_t SIMCCodeEmitter::getLitEncoding(const MCOperand &MO) const { } void SIMCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS, - SmallVectorImpl<MCFixup> &Fixups) const { + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const { uint64_t Encoding = getBinaryCodeForInstr(MI, Fixups); const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); |