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| author | Vincent Lejeune <vljn@ovi.com> | 2013-04-30 00:13:53 +0000 |
|---|---|---|
| committer | Vincent Lejeune <vljn@ovi.com> | 2013-04-30 00:13:53 +0000 |
| commit | b6379de427c009284d47c5fc764f11bbd2bf2484 (patch) | |
| tree | 69b3d80c17c755127cad9a0f61b6a4d0c1521247 /lib/Target/R600/MCTargetDesc | |
| parent | 631591e6f3e5119d8a8b1c853279bc4ac7ace4a0 (diff) | |
| download | llvm-b6379de427c009284d47c5fc764f11bbd2bf2484.tar.gz llvm-b6379de427c009284d47c5fc764f11bbd2bf2484.tar.bz2 llvm-b6379de427c009284d47c5fc764f11bbd2bf2484.tar.xz | |
R600: Turn TEX/VTX into native instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180756 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/MCTargetDesc')
| -rw-r--r-- | lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp b/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp index 0f811b1af4..36f2c1585e 100644 --- a/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp +++ b/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp @@ -142,6 +142,7 @@ void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS, if (isFCOp(MI.getOpcode())){ EmitFCInstr(MI, OS); } else if (MI.getOpcode() == AMDGPU::RETURN || + MI.getOpcode() == AMDGPU::FETCH_CLAUSE || MI.getOpcode() == AMDGPU::BUNDLE || MI.getOpcode() == AMDGPU::KILL) { return; @@ -166,10 +167,13 @@ void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS, case AMDGPU::TEX_VTX_TEXBUF : { uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups); uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset + InstWord2 |= 1 << 19; - EmitByte(INSTR_VTX, OS); + EmitByte(INSTR_NATIVE, OS); Emit(InstWord01, OS); + EmitByte(INSTR_NATIVE, OS); Emit(InstWord2, OS); + Emit((u_int32_t) 0, OS); break; } case AMDGPU::TEX_LD: @@ -241,9 +245,11 @@ void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS, SrcSelect[ELEMENT_W] << 29 | Offsets[0] << 0 | Offsets[1] << 5 | Offsets[2] << 10; - EmitByte(INSTR_TEX, OS); + EmitByte(INSTR_NATIVE, OS); Emit(Word01, OS); + EmitByte(INSTR_NATIVE, OS); Emit(Word2, OS); + Emit((u_int32_t) 0, OS); break; } case AMDGPU::CF_ALU: @@ -253,13 +259,13 @@ void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS, Emit(Inst, OS); break; } + case AMDGPU::CF_CALL_FS_EG: + case AMDGPU::CF_CALL_FS_R600: + return; case AMDGPU::CF_TC_EG: case AMDGPU::CF_VC_EG: - case AMDGPU::CF_CALL_FS_EG: case AMDGPU::CF_TC_R600: case AMDGPU::CF_VC_R600: - case AMDGPU::CF_CALL_FS_R600: - return; case AMDGPU::WHILE_LOOP_EG: case AMDGPU::END_LOOP_EG: case AMDGPU::LOOP_BREAK_EG: |