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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-06-25 21:22:18 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-06-25 21:22:18 +0000 |
| commit | 5e48a0e9ae2365a130dd1ec2e0b4beb337ab79e0 (patch) | |
| tree | 90a7974f1e0f3588375d5af2122403fee0a58c0b /lib/Target/R600/R600ExpandSpecialInstrs.cpp | |
| parent | 898b9f020d1089f679d1b1939fd6aafa9de4b411 (diff) | |
| download | llvm-5e48a0e9ae2365a130dd1ec2e0b4beb337ab79e0.tar.gz llvm-5e48a0e9ae2365a130dd1ec2e0b4beb337ab79e0.tar.bz2 llvm-5e48a0e9ae2365a130dd1ec2e0b4beb337ab79e0.tar.xz | |
R600: Use new getNamedOperandIdx function generated by TableGen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184880 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/R600ExpandSpecialInstrs.cpp')
| -rw-r--r-- | lib/Target/R600/R600ExpandSpecialInstrs.cpp | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/lib/Target/R600/R600ExpandSpecialInstrs.cpp b/lib/Target/R600/R600ExpandSpecialInstrs.cpp index 40c058fade..efc9523977 100644 --- a/lib/Target/R600/R600ExpandSpecialInstrs.cpp +++ b/lib/Target/R600/R600ExpandSpecialInstrs.cpp @@ -82,9 +82,9 @@ bool R600ExpandSpecialInstrsPass::runOnMachineFunction(MachineFunction &MF) { AMDGPU::ZERO); // src1 TII->addFlag(PredSet, 0, MO_FLAG_MASK); if (Flags & MO_FLAG_PUSH) { - TII->setImmOperand(PredSet, R600Operands::UPDATE_EXEC_MASK, 1); + TII->setImmOperand(PredSet, AMDGPU::OpName::update_exec_mask, 1); } else { - TII->setImmOperand(PredSet, R600Operands::UPDATE_PREDICATE, 1); + TII->setImmOperand(PredSet, AMDGPU::OpName::update_pred, 1); } MI.eraseFromParent(); continue; @@ -96,7 +96,7 @@ bool R600ExpandSpecialInstrsPass::runOnMachineFunction(MachineFunction &MF) { AMDGPU::ZERO, AMDGPU::ZERO); TII->addFlag(PredSet, 0, MO_FLAG_MASK); - TII->setImmOperand(PredSet, R600Operands::UPDATE_EXEC_MASK, 1); + TII->setImmOperand(PredSet, AMDGPU::OpName::update_exec_mask, 1); BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDGPU::PREDICATED_BREAK)) @@ -208,10 +208,10 @@ bool R600ExpandSpecialInstrsPass::runOnMachineFunction(MachineFunction &MF) { // While not strictly necessary from hw point of view, we force // all src operands of a dot4 inst to belong to the same slot. unsigned Src0 = BMI->getOperand( - TII->getOperandIdx(Opcode, R600Operands::SRC0)) + TII->getOperandIdx(Opcode, AMDGPU::OpName::src0)) .getReg(); unsigned Src1 = BMI->getOperand( - TII->getOperandIdx(Opcode, R600Operands::SRC1)) + TII->getOperandIdx(Opcode, AMDGPU::OpName::src1)) .getReg(); (void) Src0; (void) Src1; @@ -258,14 +258,14 @@ bool R600ExpandSpecialInstrsPass::runOnMachineFunction(MachineFunction &MF) { // T0_W = CUBE T1_Y, T1_Z for (unsigned Chan = 0; Chan < 4; Chan++) { unsigned DstReg = MI.getOperand( - TII->getOperandIdx(MI, R600Operands::DST)).getReg(); + TII->getOperandIdx(MI, AMDGPU::OpName::dst)).getReg(); unsigned Src0 = MI.getOperand( - TII->getOperandIdx(MI, R600Operands::SRC0)).getReg(); + TII->getOperandIdx(MI, AMDGPU::OpName::src0)).getReg(); unsigned Src1 = 0; // Determine the correct source registers if (!IsCube) { - int Src1Idx = TII->getOperandIdx(MI, R600Operands::SRC1); + int Src1Idx = TII->getOperandIdx(MI, AMDGPU::OpName::src1); if (Src1Idx != -1) { Src1 = MI.getOperand(Src1Idx).getReg(); } |