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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-06-23 18:00:38 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-06-23 18:00:38 +0000 |
| commit | c4471e92484328a42cfa608272ce3d214f91b285 (patch) | |
| tree | 1f4f552325ed17dc3a9fe92c149affcb26b54c04 /lib/Target/R600/R600ISelLowering.cpp | |
| parent | e564b6ed79a6ef44c63001e3d722e30ec90e1e02 (diff) | |
| download | llvm-c4471e92484328a42cfa608272ce3d214f91b285.tar.gz llvm-c4471e92484328a42cfa608272ce3d214f91b285.tar.bz2 llvm-c4471e92484328a42cfa608272ce3d214f91b285.tar.xz | |
R600/SI: Handle i64 sub.
We can handle it the same way as add
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211514 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/R600ISelLowering.cpp')
| -rw-r--r-- | lib/Target/R600/R600ISelLowering.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/lib/Target/R600/R600ISelLowering.cpp b/lib/Target/R600/R600ISelLowering.cpp index fda1ac7321..8c083262f9 100644 --- a/lib/Target/R600/R600ISelLowering.cpp +++ b/lib/Target/R600/R600ISelLowering.cpp @@ -152,6 +152,8 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) : setTargetDAGCombine(ISD::SELECT_CC); setTargetDAGCombine(ISD::INSERT_VECTOR_ELT); + setOperationAction(ISD::SUB, MVT::i64, Expand); + // These should be replaced by UDVIREM, but it does not happen automatically // during Type Legalization setOperationAction(ISD::UDIV, MVT::i64, Custom); |