diff options
| author | Vincent Lejeune <vljn@ovi.com> | 2013-05-17 16:50:32 +0000 |
|---|---|---|
| committer | Vincent Lejeune <vljn@ovi.com> | 2013-05-17 16:50:32 +0000 |
| commit | 4ed9917147b1d1f2616f7c941bbe6999b979f510 (patch) | |
| tree | 221d8b6de51be786194d310e6f95c5fdfa232624 /lib/Target/R600/R600MachineScheduler.cpp | |
| parent | d3293b49f9c7af741d2edd3062499fb50db0e89b (diff) | |
| download | llvm-4ed9917147b1d1f2616f7c941bbe6999b979f510.tar.gz llvm-4ed9917147b1d1f2616f7c941bbe6999b979f510.tar.bz2 llvm-4ed9917147b1d1f2616f7c941bbe6999b979f510.tar.xz | |
R600: Relax some vector constraints on Dot4.
Dot4 now uses 8 scalar operands instead of 2 vectors one which allows register
coalescer to remove some unneeded COPY.
This patch also defines some structures/functions that can be used to handle
every vector instructions (CUBE, Cayman special instructions...) in a similar
fashion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182126 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/R600MachineScheduler.cpp')
| -rw-r--r-- | lib/Target/R600/R600MachineScheduler.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/R600/R600MachineScheduler.cpp b/lib/Target/R600/R600MachineScheduler.cpp index c6709a8dc3..b1f4541f2a 100644 --- a/lib/Target/R600/R600MachineScheduler.cpp +++ b/lib/Target/R600/R600MachineScheduler.cpp @@ -185,6 +185,7 @@ R600SchedStrategy::AluKind R600SchedStrategy::getAluKind(SUnit *SU) const { case AMDGPU::INTERP_PAIR_XY: case AMDGPU::INTERP_PAIR_ZW: case AMDGPU::INTERP_VEC_LOAD: + case AMDGPU::DOT_4: return AluT_XYZW; case AMDGPU::COPY: if (TargetRegisterInfo::isPhysicalRegister(MI->getOperand(1).getReg())) { @@ -252,8 +253,7 @@ int R600SchedStrategy::getInstKind(SUnit* SU) { case AMDGPU::INTERP_PAIR_XY: case AMDGPU::INTERP_PAIR_ZW: case AMDGPU::INTERP_VEC_LOAD: - case AMDGPU::DOT4_eg_pseudo: - case AMDGPU::DOT4_r600_pseudo: + case AMDGPU::DOT_4: return IDAlu; case AMDGPU::TEX_VTX_CONSTBUF: case AMDGPU::TEX_VTX_TEXBUF: |