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author | Vincent Lejeune <vljn@ovi.com> | 2013-06-05 20:27:35 +0000 |
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committer | Vincent Lejeune <vljn@ovi.com> | 2013-06-05 20:27:35 +0000 |
commit | 512119770e9c32eb0b9e6196ce51917fb2e30d9f (patch) | |
tree | a573723a7bf391be08c8752e3983de46215c7e3b /lib/Target/R600/R600MachineScheduler.cpp | |
parent | 6ed30e0f0c3876df8b77c44fd3196b40903fb47d (diff) | |
download | llvm-512119770e9c32eb0b9e6196ce51917fb2e30d9f.tar.gz llvm-512119770e9c32eb0b9e6196ce51917fb2e30d9f.tar.bz2 llvm-512119770e9c32eb0b9e6196ce51917fb2e30d9f.tar.xz |
R600: Schedule copy from phys register at beginning of block
It allows regalloc pass to remove them by trivially assigning associated reg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183336 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/R600MachineScheduler.cpp')
-rw-r--r-- | lib/Target/R600/R600MachineScheduler.cpp | 32 |
1 files changed, 31 insertions, 1 deletions
diff --git a/lib/Target/R600/R600MachineScheduler.cpp b/lib/Target/R600/R600MachineScheduler.cpp index 9469e0fc6b..8524fe3c25 100644 --- a/lib/Target/R600/R600MachineScheduler.cpp +++ b/lib/Target/R600/R600MachineScheduler.cpp @@ -71,6 +71,10 @@ SUnit* R600SchedStrategy::pickNode(bool &IsTopNode) { (!AllowSwitchFromAlu && CurInstKind == IDAlu))) { // try to pick ALU SU = pickAlu(); + if (!SU && !PhysicalRegCopy.empty()) { + SU = PhysicalRegCopy.front(); + PhysicalRegCopy.erase(PhysicalRegCopy.begin()); + } if (SU) { if (CurEmitted >= InstKindLimit[IDAlu]) CurEmitted = 0; @@ -118,7 +122,22 @@ SUnit* R600SchedStrategy::pickNode(bool &IsTopNode) { return SU; } +bool IsUnScheduled(const SUnit *SU) { + return SU->isScheduled; +} + +static +void Filter(std::vector<SUnit *> &List) { + List.erase(std::remove_if(List.begin(), List.end(), IsUnScheduled), List.end()); +} + void R600SchedStrategy::schedNode(SUnit *SU, bool IsTopNode) { + if (IsTopNode) { + for (unsigned i = 0; i < AluLast; i++) { + Filter(Available[i]); + Filter(Pending[i]); + } + } if (NextInstKind != CurInstKind) { DEBUG(dbgs() << "Instruction Type Switch\n"); @@ -157,13 +176,24 @@ void R600SchedStrategy::schedNode(SUnit *SU, bool IsTopNode) { } } +static bool +isPhysicalRegCopy(MachineInstr *MI) { + if (MI->getOpcode() != AMDGPU::COPY) + return false; + + return !TargetRegisterInfo::isVirtualRegister(MI->getOperand(1).getReg()); +} + void R600SchedStrategy::releaseTopNode(SUnit *SU) { DEBUG(dbgs() << "Top Releasing ";SU->dump(DAG);); - } void R600SchedStrategy::releaseBottomNode(SUnit *SU) { DEBUG(dbgs() << "Bottom Releasing ";SU->dump(DAG);); + if (isPhysicalRegCopy(SU->getInstr())) { + PhysicalRegCopy.push_back(SU); + return; + } int IK = getInstKind(SU); |