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| author | Andrew Trick <atrick@apple.com> | 2013-12-28 21:56:47 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2013-12-28 21:56:47 +0000 |
| commit | a38b0de893c3a12b3c2ce899d7f9c96e2dc10395 (patch) | |
| tree | dc668d3c63ed5bf26650eedfbd3dc9fcb9b07902 /lib/Target/R600/R600MachineScheduler.cpp | |
| parent | 4fb3d630a915620ae6ba62e1825123577426e33e (diff) | |
| download | llvm-a38b0de893c3a12b3c2ce899d7f9c96e2dc10395.tar.gz llvm-a38b0de893c3a12b3c2ce899d7f9c96e2dc10395.tar.bz2 llvm-a38b0de893c3a12b3c2ce899d7f9c96e2dc10395.tar.xz | |
Factor MI-Sched in preparation for post-ra scheduling support.
Factor the MachineFunctionPass into MachineSchedulerBase.
Split the DAG class into ScheduleDAGMI and SchedulerDAGMILive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198119 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/R600MachineScheduler.cpp')
| -rw-r--r-- | lib/Target/R600/R600MachineScheduler.cpp | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/lib/Target/R600/R600MachineScheduler.cpp b/lib/Target/R600/R600MachineScheduler.cpp index da2a4d862e..d3ffb506f1 100644 --- a/lib/Target/R600/R600MachineScheduler.cpp +++ b/lib/Target/R600/R600MachineScheduler.cpp @@ -24,8 +24,8 @@ using namespace llvm; void R600SchedStrategy::initialize(ScheduleDAGMI *dag) { - - DAG = dag; + assert(dag->hasVRegLiveness() && "R600SchedStrategy needs vreg liveness"); + DAG = static_cast<ScheduleDAGMILive*>(dag); TII = static_cast<const R600InstrInfo*>(DAG->TII); TRI = static_cast<const R600RegisterInfo*>(DAG->TRI); VLIW5 = !DAG->MF.getTarget().getSubtarget<AMDGPUSubtarget>().hasCaymanISA(); @@ -72,7 +72,7 @@ SUnit* R600SchedStrategy::pickNode(bool &IsTopNode) { // OpenCL Programming Guide : // The approx. number of WF that allows TEX inst to hide ALU inst is : // 500 (cycles for TEX) / (AluFetchRatio * 8 (cycles for ALU)) - float ALUFetchRationEstimate = + float ALUFetchRationEstimate = (AluInstCount + AvailablesAluCount() + Pending[IDAlu].size()) / (FetchInstCount + Available[IDFetch].size()); unsigned NeededWF = 62.5f / ALUFetchRationEstimate; @@ -464,4 +464,3 @@ SUnit* R600SchedStrategy::pickOther(int QID) { } return SU; } - |