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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-09-12 02:55:06 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-09-12 02:55:06 +0000 |
| commit | ac779b8494ad3d2f2ea40cb566552c0fb1b17363 (patch) | |
| tree | 457837e32c2be033d5ef5719cdf5bcb2b5467989 /lib/Target/R600/R600MachineScheduler.cpp | |
| parent | 8f2f86f8899fcd98405005dbd6195ffa606f5d15 (diff) | |
| download | llvm-ac779b8494ad3d2f2ea40cb566552c0fb1b17363.tar.gz llvm-ac779b8494ad3d2f2ea40cb566552c0fb1b17363.tar.bz2 llvm-ac779b8494ad3d2f2ea40cb566552c0fb1b17363.tar.xz | |
R600: Don't use trans slot for instructions that read LDS source registers
This fixes some regressions in the piglit local memory store tests
introduced by recent commits which made the scheduler aware of the trans
slot.
It's not possible to test this using lit, because there is no way to
determine from the assembly dumps whether or not an instruction is in
the trans slot.
Even if this were possible, the test would be highly sensitive to
changes in the scheduler and might generate confusing false negatives.
Reviewed-by: Vincent Lejeune<vljn at ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190574 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/R600MachineScheduler.cpp')
| -rw-r--r-- | lib/Target/R600/R600MachineScheduler.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/lib/Target/R600/R600MachineScheduler.cpp b/lib/Target/R600/R600MachineScheduler.cpp index 0499dd52d9..6c26d9ece4 100644 --- a/lib/Target/R600/R600MachineScheduler.cpp +++ b/lib/Target/R600/R600MachineScheduler.cpp @@ -314,6 +314,10 @@ R600SchedStrategy::AluKind R600SchedStrategy::getAluKind(SUnit *SU) const { if (regBelongsToClass(DestReg, &AMDGPU::R600_Reg128RegClass)) return AluT_XYZW; + // LDS src registers cannot be used in the Trans slot. + if (TII->readsLDSSrcReg(MI)) + return AluT_XYZW; + return AluAny; } |