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author | Tom Stellard <thomas.stellard@amd.com> | 2013-06-28 15:47:08 +0000 |
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committer | Tom Stellard <thomas.stellard@amd.com> | 2013-06-28 15:47:08 +0000 |
commit | e3d4cbc7d25061441adafa47450a31571c87bf85 (patch) | |
tree | 1bb21b2cbfd7ca47d98b8da9c2b59dfed92700f9 /lib/Target/R600/R600MachineScheduler.cpp | |
parent | cedcfee405a22b245e869abe8609f094df34085a (diff) | |
download | llvm-e3d4cbc7d25061441adafa47450a31571c87bf85.tar.gz llvm-e3d4cbc7d25061441adafa47450a31571c87bf85.tar.bz2 llvm-e3d4cbc7d25061441adafa47450a31571c87bf85.tar.xz |
R600: Add local memory support via LDS
Reviewed-by: Vincent Lejeune<vljn at ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185162 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/R600MachineScheduler.cpp')
-rw-r--r-- | lib/Target/R600/R600MachineScheduler.cpp | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/lib/Target/R600/R600MachineScheduler.cpp b/lib/Target/R600/R600MachineScheduler.cpp index acc1b4d6ee..7e28f9dde4 100644 --- a/lib/Target/R600/R600MachineScheduler.cpp +++ b/lib/Target/R600/R600MachineScheduler.cpp @@ -278,6 +278,10 @@ R600SchedStrategy::AluKind R600SchedStrategy::getAluKind(SUnit *SU) const { return AluT_XYZW; } + if (TII->isLDSInstr(MI->getOpcode())) { + return AluT_X; + } + // Is the result already assigned to a channel ? unsigned DestSubReg = MI->getOperand(0).getSubReg(); switch (DestSubReg) { @@ -371,14 +375,18 @@ void R600SchedStrategy::PrepareNextSlot() { } void R600SchedStrategy::AssignSlot(MachineInstr* MI, unsigned Slot) { - unsigned DestReg = MI->getOperand(0).getReg(); + int DstIndex = TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst); + if (DstIndex == -1) { + return; + } + unsigned DestReg = MI->getOperand(DstIndex).getReg(); // PressureRegister crashes if an operand is def and used in the same inst // and we try to constraint its regclass for (MachineInstr::mop_iterator It = MI->operands_begin(), E = MI->operands_end(); It != E; ++It) { MachineOperand &MO = *It; if (MO.isReg() && !MO.isDef() && - MO.getReg() == MI->getOperand(0).getReg()) + MO.getReg() == DestReg) return; } // Constrains the regclass of DestReg to assign it to Slot |