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author | Owen Anderson <resistor@mac.com> | 2014-03-13 23:12:04 +0000 |
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committer | Owen Anderson <resistor@mac.com> | 2014-03-13 23:12:04 +0000 |
commit | bf63022492e54c8abe7c8d8c8448661342294f46 (patch) | |
tree | afd0498b2b0da324ad89111ea83faf705400dec9 /lib/Target/R600/R600OptimizeVectorRegisters.cpp | |
parent | d3fc1be4f634df136220ffc6e2ec381ae3f55c31 (diff) | |
download | llvm-bf63022492e54c8abe7c8d8c8448661342294f46.tar.gz llvm-bf63022492e54c8abe7c8d8c8448661342294f46.tar.bz2 llvm-bf63022492e54c8abe7c8d8c8448661342294f46.tar.xz |
Phase 2 of the great MachineRegisterInfo cleanup. This time, we're changing
operator* on the by-operand iterators to return a MachineOperand& rather than
a MachineInstr&. At this point they almost behave like normal iterators!
Again, this requires making some existing loops more verbose, but should pave
the way for the big range-based for-loop cleanups in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203865 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/R600OptimizeVectorRegisters.cpp')
-rw-r--r-- | lib/Target/R600/R600OptimizeVectorRegisters.cpp | 17 |
1 files changed, 9 insertions, 8 deletions
diff --git a/lib/Target/R600/R600OptimizeVectorRegisters.cpp b/lib/Target/R600/R600OptimizeVectorRegisters.cpp index 49a90658a7..767e5e37a4 100644 --- a/lib/Target/R600/R600OptimizeVectorRegisters.cpp +++ b/lib/Target/R600/R600OptimizeVectorRegisters.cpp @@ -46,8 +46,8 @@ namespace { static bool isImplicitlyDef(MachineRegisterInfo &MRI, unsigned Reg) { - for (MachineRegisterInfo::def_iterator It = MRI.def_begin(Reg), - E = MRI.def_end(); It != E; ++It) { + for (MachineRegisterInfo::def_instr_iterator It = MRI.def_instr_begin(Reg), + E = MRI.def_instr_end(); It != E; ++It) { return (*It).isImplicitDef(); } if (MRI.isReserved(Reg)) { @@ -213,8 +213,8 @@ MachineInstr *R600VectorRegMerger::RebuildVector( DEBUG(dbgs() << " ->"; Pos->dump();); DEBUG(dbgs() << " Updating Swizzle:\n"); - for (MachineRegisterInfo::use_iterator It = MRI->use_begin(Reg), - E = MRI->use_end(); It != E; ++It) { + for (MachineRegisterInfo::use_instr_iterator It = MRI->use_instr_begin(Reg), + E = MRI->use_instr_end(); It != E; ++It) { DEBUG(dbgs() << " ";(*It).dump(); dbgs() << " ->"); SwizzleInput(*It, RemapChan); DEBUG((*It).dump()); @@ -261,8 +261,8 @@ void R600VectorRegMerger::SwizzleInput(MachineInstr &MI, } bool R600VectorRegMerger::areAllUsesSwizzeable(unsigned Reg) const { - for (MachineRegisterInfo::use_iterator It = MRI->use_begin(Reg), - E = MRI->use_end(); It != E; ++It) { + for (MachineRegisterInfo::use_instr_iterator It = MRI->use_instr_begin(Reg), + E = MRI->use_instr_end(); It != E; ++It) { if (!canSwizzle(*It)) return false; } @@ -328,8 +328,9 @@ bool R600VectorRegMerger::runOnMachineFunction(MachineFunction &Fn) { if (MI->getOpcode() != AMDGPU::REG_SEQUENCE) { if (TII->get(MI->getOpcode()).TSFlags & R600_InstFlag::TEX_INST) { unsigned Reg = MI->getOperand(1).getReg(); - for (MachineRegisterInfo::def_iterator It = MRI->def_begin(Reg), - E = MRI->def_end(); It != E; ++It) { + for (MachineRegisterInfo::def_instr_iterator + It = MRI->def_instr_begin(Reg), E = MRI->def_instr_end(); + It != E; ++It) { RemoveMI(&(*It)); } } |