diff options
| author | Vincent Lejeune <vljn@ovi.com> | 2013-05-17 16:50:09 +0000 |
|---|---|---|
| committer | Vincent Lejeune <vljn@ovi.com> | 2013-05-17 16:50:09 +0000 |
| commit | 4109bd8829c2736016a2eb9777ea0b52ba2f7d5c (patch) | |
| tree | 06f66d96519abb198a3e866cb9e177ddbfbac52c /lib/Target/R600/R600RegisterInfo.td | |
| parent | 25c209e9a262b623deca60fb6b886907e22c941b (diff) | |
| download | llvm-4109bd8829c2736016a2eb9777ea0b52ba2f7d5c.tar.gz llvm-4109bd8829c2736016a2eb9777ea0b52ba2f7d5c.tar.bz2 llvm-4109bd8829c2736016a2eb9777ea0b52ba2f7d5c.tar.xz | |
R600: Rename 128 bit registers.
Almost all instructions that takes a 128 bits reg as input (fetch, export...)
have the abilities to swizzle their argument and output. Instead of printing
default swizzle for each 128 bits reg, rename T*.XYZW to T* and let instructions
print potentially optimized swizzles themselves.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182124 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/R600RegisterInfo.td')
| -rw-r--r-- | lib/Target/R600/R600RegisterInfo.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/R600/R600RegisterInfo.td b/lib/Target/R600/R600RegisterInfo.td index bfc546bb99..df6004bd04 100644 --- a/lib/Target/R600/R600RegisterInfo.td +++ b/lib/Target/R600/R600RegisterInfo.td @@ -35,7 +35,7 @@ foreach Index = 0-127 in { Chan>; } // 128-bit Temporary Registers - def T#Index#_XYZW : R600Reg_128 <"T"#Index#".XYZW", + def T#Index#_XYZW : R600Reg_128 <"T"#Index#"", [!cast<Register>("T"#Index#"_X"), !cast<Register>("T"#Index#"_Y"), !cast<Register>("T"#Index#"_Z"), |