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author | Tom Stellard <thomas.stellard@amd.com> | 2014-06-24 23:33:04 +0000 |
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committer | Tom Stellard <thomas.stellard@amd.com> | 2014-06-24 23:33:04 +0000 |
commit | 78d1e952014fd0ed58528ad3a65639d6b6d1077e (patch) | |
tree | ef178aaa7358f9e0ad13496685a906907a53343b /lib/Target/R600/SIISelLowering.cpp | |
parent | e572ec68d261d37faeb7129d1b3fdb68c4f8d6be (diff) | |
download | llvm-78d1e952014fd0ed58528ad3a65639d6b6d1077e.tar.gz llvm-78d1e952014fd0ed58528ad3a65639d6b6d1077e.tar.bz2 llvm-78d1e952014fd0ed58528ad3a65639d6b6d1077e.tar.xz |
R600: Promote i64 stores to v2i32
Now we need only one 64-bit pattern for stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211643 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/SIISelLowering.cpp')
-rw-r--r-- | lib/Target/R600/SIISelLowering.cpp | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp index 1a61568b5d..29e4b98e84 100644 --- a/lib/Target/R600/SIISelLowering.cpp +++ b/lib/Target/R600/SIISelLowering.cpp @@ -98,7 +98,6 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) : setOperationAction(ISD::STORE, MVT::i1, Custom); setOperationAction(ISD::STORE, MVT::i32, Custom); - setOperationAction(ISD::STORE, MVT::i64, Custom); setOperationAction(ISD::STORE, MVT::v2i32, Custom); setOperationAction(ISD::STORE, MVT::v4i32, Custom); @@ -912,6 +911,12 @@ SDValue SITargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const { StoreSDNode *Store = cast<StoreSDNode>(Op); EVT VT = Store->getMemoryVT(); + // These stores are legal. + if (Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS && + VT.isVector() && VT.getVectorNumElements() == 2 && + VT.getVectorElementType() == MVT::i32) + return SDValue(); + SDValue Ret = AMDGPUTargetLowering::LowerSTORE(Op, DAG); if (Ret.getNode()) return Ret; |