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author | Tom Stellard <thomas.stellard@amd.com> | 2014-05-02 15:41:42 +0000 |
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committer | Tom Stellard <thomas.stellard@amd.com> | 2014-05-02 15:41:42 +0000 |
commit | 9b226260681e9ee96b431b1cb75924e14d59fb0a (patch) | |
tree | f7d896b30e1d71996f98e6b5b4048732da500124 /lib/Target/R600/SIRegisterInfo.cpp | |
parent | ecc189660078eb63e8fc463a7d5872f220d15789 (diff) | |
download | llvm-9b226260681e9ee96b431b1cb75924e14d59fb0a.tar.gz llvm-9b226260681e9ee96b431b1cb75924e14d59fb0a.tar.bz2 llvm-9b226260681e9ee96b431b1cb75924e14d59fb0a.tar.xz |
R600/SI: Only create one instruction when spilling/restoring register v3
The register spiller assumes that only one new instruction is created
when spilling and restoring registers, so we need to emit pseudo
instructions for vector register spills and lower them after
register allocation.
v2:
- Fix calculation of lane index
- Extend VGPR liveness to end of program.
v3:
- Use SIMM16 field of S_NOP to specify multiple NOPs.
https://bugs.freedesktop.org/show_bug.cgi?id=75005
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207843 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/SIRegisterInfo.cpp')
-rw-r--r-- | lib/Target/R600/SIRegisterInfo.cpp | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/lib/Target/R600/SIRegisterInfo.cpp b/lib/Target/R600/SIRegisterInfo.cpp index 5897fbca94..8dc9a05799 100644 --- a/lib/Target/R600/SIRegisterInfo.cpp +++ b/lib/Target/R600/SIRegisterInfo.cpp @@ -129,3 +129,10 @@ const TargetRegisterClass *SIRegisterInfo::getSubRegClass( return &AMDGPU::VGPR_32RegClass; } } + +unsigned SIRegisterInfo::getPhysRegSubReg(unsigned Reg, + const TargetRegisterClass *SubRC, + unsigned Channel) const { + unsigned Index = getHWRegIndex(Reg); + return SubRC->getRegister(Index + Channel); +} |