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authorTom Stellard <thomas.stellard@amd.com>2013-11-27 21:23:39 +0000
committerTom Stellard <thomas.stellard@amd.com>2013-11-27 21:23:39 +0000
commit8a6b7df6f8d4eda9680a22b204967f70d8bbf398 (patch)
tree24f415aad0336d1e39b8beb53d1021775d6c74dc /lib/Target/R600
parentaa6ec15caff3658bad00a2185d838ea067c660d8 (diff)
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R600: Expand vector FABS
NOTE: This is a candidate for the 3.4 branch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195881 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600')
-rw-r--r--lib/Target/R600/AMDGPUISelLowering.cpp1
1 files changed, 1 insertions, 0 deletions
diff --git a/lib/Target/R600/AMDGPUISelLowering.cpp b/lib/Target/R600/AMDGPUISelLowering.cpp
index f2a6aab9cd..c4d75ffa0d 100644
--- a/lib/Target/R600/AMDGPUISelLowering.cpp
+++ b/lib/Target/R600/AMDGPUISelLowering.cpp
@@ -179,6 +179,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
for (unsigned int x = 0; x < NumFloatTypes; ++x) {
MVT::SimpleValueType VT = FloatTypes[x];
+ setOperationAction(ISD::FABS, VT, Expand);
setOperationAction(ISD::FADD, VT, Expand);
setOperationAction(ISD::FDIV, VT, Expand);
setOperationAction(ISD::FFLOOR, VT, Expand);