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author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2013-11-18 20:09:50 +0000 |
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committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2013-11-18 20:09:50 +0000 |
commit | 9bc4b2c0dae143e72624984dfd5e3a4ff2e95eb2 (patch) | |
tree | 5baea4374ebd24584f024cd04465c16534f62fbe /lib/Target/R600 | |
parent | e64a2896094be370f5ca3d755f62c762fb94b37a (diff) | |
download | llvm-9bc4b2c0dae143e72624984dfd5e3a4ff2e95eb2.tar.gz llvm-9bc4b2c0dae143e72624984dfd5e3a4ff2e95eb2.tar.bz2 llvm-9bc4b2c0dae143e72624984dfd5e3a4ff2e95eb2.tar.xz |
R600/SI: Fix multiple SGPR reads when using VCC.
No other SGPR operands are allowed, so if VCC is
used, move the other to a VGPR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195041 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600')
-rw-r--r-- | lib/Target/R600/SIInstrInfo.cpp | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/lib/Target/R600/SIInstrInfo.cpp b/lib/Target/R600/SIInstrInfo.cpp index a5d4e1ab06..7f23ecf91f 100644 --- a/lib/Target/R600/SIInstrInfo.cpp +++ b/lib/Target/R600/SIInstrInfo.cpp @@ -417,6 +417,7 @@ void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const { MachineOperand &MO = MI->getOperand(OpIdx); MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass; + // XXX - This shouldn't be VSrc const TargetRegisterClass *RC = RI.getRegClass(RCID); unsigned Opcode = AMDGPU::V_MOV_B32_e32; if (MO.isReg()) { @@ -442,8 +443,24 @@ void SIInstrInfo::legalizeOperands(MachineInstr *MI) const { // Legalize VOP2 if (isVOP2(MI->getOpcode()) && Src1Idx != -1) { + MachineOperand &Src0 = MI->getOperand(Src0Idx); MachineOperand &Src1 = MI->getOperand(Src1Idx); + // If the instruction implicitly reads VCC, we can't have any SGPR operands, + // so move any. + bool ReadsVCC = MI->readsRegister(AMDGPU::VCC, &RI); + if (ReadsVCC && Src0.isReg() && + RI.isSGPRClass(MRI.getRegClass(Src0.getReg()))) { + legalizeOpWithMove(MI, Src0Idx); + return; + } + + if (ReadsVCC && Src1.isReg() && + RI.isSGPRClass(MRI.getRegClass(Src1.getReg()))) { + legalizeOpWithMove(MI, Src1Idx); + return; + } + // Legalize VOP2 instructions where src1 is not a VGPR. An SGPR input must // be the first operand, and there can only be one. if (Src1.isImm() || Src1.isFPImm() || @@ -456,6 +473,7 @@ void SIInstrInfo::legalizeOperands(MachineInstr *MI) const { } } + // XXX - Do any VOP3 instructions read VCC? // Legalize VOP3 if (isVOP3(MI->getOpcode())) { int VOP3Idx[3] = {Src0Idx, Src1Idx, Src2Idx}; |