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| author | Craig Topper <craig.topper@gmail.com> | 2014-06-19 06:10:58 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2014-06-19 06:10:58 +0000 |
| commit | bd01df2487e451fcdac23875f2a101b8e93fbe6e (patch) | |
| tree | a934bc910cfd97051ee218e3cf0ce8521d667a79 /lib/Target/R600 | |
| parent | 64429cefba00547d37b50383536a62047fd93380 (diff) | |
| download | llvm-bd01df2487e451fcdac23875f2a101b8e93fbe6e.tar.gz llvm-bd01df2487e451fcdac23875f2a101b8e93fbe6e.tar.bz2 llvm-bd01df2487e451fcdac23875f2a101b8e93fbe6e.tar.xz | |
Convert some assert(0) to llvm_unreachable or fold an 'if' condition into the assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211254 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600')
| -rw-r--r-- | lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp | 14 |
1 files changed, 5 insertions, 9 deletions
diff --git a/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp b/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp index 5e7cefed0a..dc1344fb8d 100644 --- a/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp +++ b/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp @@ -172,17 +172,13 @@ uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixup, const MCSubtargetInfo &STI) const { if (MO.isReg()) { - if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags)) { + if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags)) return MRI.getEncodingValue(MO.getReg()); - } else { - return getHWReg(MO.getReg()); - } - } else if (MO.isImm()) { - return MO.getImm(); - } else { - assert(0); - return 0; + return getHWReg(MO.getReg()); } + + assert(MO.isImm()); + return MO.getImm(); } #include "AMDGPUGenMCCodeEmitter.inc" |