update some notes slightly

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89913 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 5 insertions, 3 deletions

diff --git a/lib/Target/README.txt b/lib/Target/README.txt
index aad621f440..6d90f05a46 100644
--- a/lib/Target/README.txt
+++ b/lib/Target/README.txt
@@ -220,7 +220,7 @@ so cool to turn it into something like:
 ... which would only do one 32-bit XOR per loop iteration instead of two.
 
 It would also be nice to recognize the reg->size doesn't alias reg->node[i], but
-alas.
+this requires TBAA.
 
 //===---------------------------------------------------------------------===//
 
@@ -280,6 +280,9 @@ unsigned int popcount(unsigned int input) {
   return count;
 }
 
+This is a form of idiom recognition for loops, the same thing that could be
+useful for recognizing memset/memcpy.
+
 //===---------------------------------------------------------------------===//
 
 These should turn into single 16-bit (unaligned?) loads on little/big endian
@@ -343,7 +346,7 @@ PHI Slicing could be extended to do this.
 
 //===---------------------------------------------------------------------===//
 
-LSR should know what GPR types a target has.  This code:
+LSR should know what GPR types a target has from TargetData.  This code:
 
 volatile short X, Y; // globals
 
@@ -369,7 +372,6 @@ LBB1_2:
 
 LSR should reuse the "+" IV for the exit test.
 
-
 //===---------------------------------------------------------------------===//
 
 Tail call elim should be more aggressive, checking to see if the call is