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authorBrian Gaeke <gaeke@uiuc.edu>2004-09-29 03:24:34 +0000
committerBrian Gaeke <gaeke@uiuc.edu>2004-09-29 03:24:34 +0000
commit15b2838035e5668ba4b756319204de7dec9a51d8 (patch)
tree38f185da68151af6feb46cf91ae1cb0d28eb25f5 /lib/Target/Sparc/FPMover.cpp
parentb5ddea5d24a4346e2c7251d0482622bce83accb8 (diff)
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Pass which converts FpMOVD (double move pseudoinstructions) to pairs
of FMOVS instrs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16570 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Sparc/FPMover.cpp')
-rw-r--r--lib/Target/Sparc/FPMover.cpp91
1 files changed, 91 insertions, 0 deletions
diff --git a/lib/Target/Sparc/FPMover.cpp b/lib/Target/Sparc/FPMover.cpp
new file mode 100644
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+++ b/lib/Target/Sparc/FPMover.cpp
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+//===-- FPMover.cpp - SparcV8 double-precision floating point move fixer --===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// Turns FpMOVD instructions into FMOVS pairs after regalloc.
+//
+//===----------------------------------------------------------------------===//
+
+#include "SparcV8.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/ADT/Statistic.h"
+
+using namespace llvm;
+
+namespace {
+ Statistic<> NumFpMOVDs ("fpmover", "# FpMOVD instructions translated");
+
+ struct FPMover : public MachineFunctionPass {
+ /// Target machine description which we query for reg. names, data
+ /// layout, etc.
+ ///
+ TargetMachine &TM;
+
+ FPMover (TargetMachine &tm) : TM (tm) { }
+
+ virtual const char *getPassName () const {
+ return "SparcV8 Double-FP Move Fixer";
+ }
+
+ bool runOnMachineBasicBlock (MachineBasicBlock &MBB);
+ bool runOnMachineFunction (MachineFunction &F) {
+ bool Changed = false;
+ for (MachineFunction::iterator FI = F.begin (), FE = F.end ();
+ FI != FE; ++FI)
+ Changed |= runOnMachineBasicBlock (*FI);
+ return Changed;
+ }
+
+ };
+} // end of anonymous namespace
+
+/// createSparcV8FPMoverPass - Returns a pass that turns FpMOVD
+/// instructions into FMOVS instructions
+///
+FunctionPass *llvm::createSparcV8FPMoverPass (TargetMachine &tm) {
+ return new FPMover (tm);
+}
+
+static void doubleToSingleRegPair(unsigned doubleReg, unsigned &singleReg1, unsigned &singleReg2) {
+ const unsigned EvenHalvesOfPairs[] = { V8::F0, V8::F2, V8::F4, V8::F6, V8::F8, V8::F10, V8::F12, V8::F14, V8::F16, V8::F18, V8::F20, V8::F22, V8::F24, V8::F26, V8::F28, V8::F30 };
+ const unsigned OddHalvesOfPairs[] = { V8::F1, V8::F3, V8::F5, V8::F7, V8::F9, V8::F11, V8::F13, V8::F15, V8::F17, V8::F19, V8::F21, V8::F23, V8::F25, V8::F27, V8::F29, V8::F31 };
+ const unsigned DoubleRegsInOrder[] = { V8::D0, V8::D1, V8::D2, V8::D3, V8::D4, V8::D5, V8::D6, V8::D7, V8::D8, V8::D9, V8::D10, V8::D11, V8::D12, V8::D13, V8::D14, V8::D15 };
+ for (unsigned i = 0; i < sizeof(DoubleRegsInOrder)/sizeof(unsigned); ++i)
+ if (DoubleRegsInOrder[i] == doubleReg) {
+ singleReg1 = EvenHalvesOfPairs[i];
+ singleReg2 = OddHalvesOfPairs[i];
+ return;
+ }
+ assert (0 && "Can't find reg");
+}
+
+/// runOnMachineBasicBlock - Fixup FpMOVD instructions in this MBB.
+///
+bool FPMover::runOnMachineBasicBlock (MachineBasicBlock &MBB) {
+ bool Changed = false;
+ for (MachineBasicBlock::iterator I = MBB.begin (); I != MBB.end (); ++I)
+ if (V8::FpMOVD == I->getOpcode()) {
+ I->setOpcode (V8::FMOVS);
+ unsigned DestReg = I->getOperand(0).getReg();
+ unsigned SrcReg = I->getOperand(1).getReg();
+ unsigned NewSrcReg0, NewSrcReg1;
+ unsigned NewDestReg0, NewDestReg1;
+ doubleToSingleRegPair (DestReg, NewDestReg0, NewDestReg1);
+ doubleToSingleRegPair (SrcReg, NewSrcReg0, NewSrcReg1);
+ I->SetMachineOperandReg (0, NewDestReg0);
+ I->SetMachineOperandReg (1, NewSrcReg0);
+ // Insert copy for the other half of the double:
+ MachineBasicBlock::iterator J = I;
+ ++J;
+ BuildMI (MBB, J, V8::FMOVS, 1, NewDestReg1).addReg(NewSrcReg1);
+ ++NumFpMOVDs;
+ Changed = true;
+ }
+ return Changed;
+}