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author | Venkatraman Govindaraju <venkatra@cs.wisc.edu> | 2013-09-21 23:51:08 +0000 |
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committer | Venkatraman Govindaraju <venkatra@cs.wisc.edu> | 2013-09-21 23:51:08 +0000 |
commit | 20b5879e0ec5c926c3b636ad36d5b6cfb278f736 (patch) | |
tree | fba9f58a36701b571eb9c5327b34ec9a4a55a808 /lib/Target/Sparc/SparcISelLowering.cpp | |
parent | 1ce1525ed453aea78d17f28ec3c353d0cde5341f (diff) | |
download | llvm-20b5879e0ec5c926c3b636ad36d5b6cfb278f736.tar.gz llvm-20b5879e0ec5c926c3b636ad36d5b6cfb278f736.tar.bz2 llvm-20b5879e0ec5c926c3b636ad36d5b6cfb278f736.tar.xz |
[Sparc] Fix lowering FABS on fp128 (long double) on pre-v9 targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191154 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Sparc/SparcISelLowering.cpp')
-rw-r--r-- | lib/Target/Sparc/SparcISelLowering.cpp | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/lib/Target/Sparc/SparcISelLowering.cpp b/lib/Target/Sparc/SparcISelLowering.cpp index 641ab6cd25..2260fe48b3 100644 --- a/lib/Target/Sparc/SparcISelLowering.cpp +++ b/lib/Target/Sparc/SparcISelLowering.cpp @@ -2160,12 +2160,12 @@ static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, return RetAddr; } -static SDValue LowerF64Op(SDValue Op, SelectionDAG &DAG) +static SDValue LowerF64Op(SDValue Op, SelectionDAG &DAG, unsigned opcode) { SDLoc dl(Op); assert(Op.getValueType() == MVT::f64 && "LowerF64Op called on non-double!"); - assert(Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS); + assert(opcode == ISD::FNEG || opcode == ISD::FABS); // Lower fneg/fabs on f64 to fneg/fabs on f32. // fneg f64 => fneg f32:sub_even, fmov f32:sub_odd. @@ -2177,7 +2177,7 @@ static SDValue LowerF64Op(SDValue Op, SelectionDAG &DAG) SDValue Lo32 = DAG.getTargetExtractSubreg(SP::sub_odd, dl, MVT::f32, SrcReg64); - Hi32 = DAG.getNode(Op.getOpcode(), dl, MVT::f32, Hi32); + Hi32 = DAG.getNode(opcode, dl, MVT::f32, Hi32); SDValue DstReg64 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, MVT::f64), 0); @@ -2280,7 +2280,7 @@ static SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool is64Bit) { if (Op.getValueType() == MVT::f64) - return LowerF64Op(Op, DAG); + return LowerF64Op(Op, DAG, ISD::FNEG); if (Op.getValueType() == MVT::f128) return TLI.LowerF128Op(Op, DAG, ((is64Bit) ? "_Qp_neg" : "_Q_neg"), 1); return Op; @@ -2288,7 +2288,7 @@ static SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG, static SDValue LowerFABS(SDValue Op, SelectionDAG &DAG, bool isV9) { if (Op.getValueType() == MVT::f64) - return LowerF64Op(Op, DAG); + return LowerF64Op(Op, DAG, ISD::FABS); if (Op.getValueType() != MVT::f128) return Op; @@ -2304,7 +2304,7 @@ static SDValue LowerFABS(SDValue Op, SelectionDAG &DAG, bool isV9) { if (isV9) Hi64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Hi64); else - Hi64 = LowerF64Op(Op, DAG); + Hi64 = LowerF64Op(Hi64, DAG, ISD::FABS); SDValue DstReg128 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, MVT::f128), 0); |