Add rudimentary support for 'r' register operand

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57359 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 18 insertions, 11 deletions

diff --git a/lib/Target/Sparc/SparcISelLowering.h b/lib/Target/Sparc/SparcISelLowering.h
index d71f51c6e6..ea3171d027 100644
--- a/lib/Target/Sparc/SparcISelLowering.h
+++ b/lib/Target/Sparc/SparcISelLowering.h
@@ -28,41 +28,48 @@ namespace llvm {
       BRFCC,       // Branch to dest on fcc condition
       SELECT_ICC,  // Select between two values using the current ICC flags.
       SELECT_FCC,  // Select between two values using the current FCC flags.
-      
+
       Hi, Lo,      // Hi/Lo operations, typically on a global address.
-      
+
       FTOI,        // FP to Int within a FP register.
       ITOF,        // Int to FP within a FP register.
-      
+
       CALL,        // A call instruction.
       RET_FLAG     // Return with a flag operand.
     };
   }
-  
+
   class SparcTargetLowering : public TargetLowering {
     int VarArgsFrameOffset;   // Frame offset to start of varargs area.
   public:
     SparcTargetLowering(TargetMachine &TM);
     virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
-    
+
     int getVarArgsFrameOffset() const { return VarArgsFrameOffset; }
-    
-    /// computeMaskedBitsForTargetNode - Determine which of the bits specified 
-    /// in Mask are known to be either zero or one and return them in the 
+
+    /// computeMaskedBitsForTargetNode - Determine which of the bits specified
+    /// in Mask are known to be either zero or one and return them in the
     /// KnownZero/KnownOne bitsets.
     virtual void computeMaskedBitsForTargetNode(const SDValue Op,
                                                 const APInt &Mask,
-                                                APInt &KnownZero, 
+                                                APInt &KnownZero,
                                                 APInt &KnownOne,
                                                 const SelectionDAG &DAG,
                                                 unsigned Depth = 0) const;
-    
+
     virtual void LowerArguments(Function &F, SelectionDAG &DAG,
                                 SmallVectorImpl<SDValue> &ArgValues);
     virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
                                                         MachineBasicBlock *MBB);
-    
+
     virtual const char *getTargetNodeName(unsigned Opcode) const;
+
+    ConstraintType getConstraintType(const std::string &Constraint) const;
+    std::pair<unsigned, const TargetRegisterClass*>
+    getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const;
+    std::vector<unsigned>
+    getRegClassForInlineAsmConstraint(const std::string &Constraint,
+                                      MVT VT) const;
   };
 } // end namespace llvm