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| author | Venkatraman Govindaraju <venkatra@cs.wisc.edu> | 2014-03-01 07:46:33 +0000 |
|---|---|---|
| committer | Venkatraman Govindaraju <venkatra@cs.wisc.edu> | 2014-03-01 07:46:33 +0000 |
| commit | 06f2e69c2f43b22b6030b1e8992a636f5fee88d8 (patch) | |
| tree | fed694cbda5e1e7c4abefc823706384788913836 /lib/Target/Sparc/SparcInstrInfo.td | |
| parent | f8bc17fadc8f170c1126328d203f0dab78960137 (diff) | |
| download | llvm-06f2e69c2f43b22b6030b1e8992a636f5fee88d8.tar.gz llvm-06f2e69c2f43b22b6030b1e8992a636f5fee88d8.tar.bz2 llvm-06f2e69c2f43b22b6030b1e8992a636f5fee88d8.tar.xz | |
[Sparc] Add support to disassemble sparc memory instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202575 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Sparc/SparcInstrInfo.td')
| -rw-r--r-- | lib/Target/Sparc/SparcInstrInfo.td | 42 |
1 files changed, 26 insertions, 16 deletions
diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td index ae10ca0bd4..57b692562e 100644 --- a/lib/Target/Sparc/SparcInstrInfo.td +++ b/lib/Target/Sparc/SparcInstrInfo.td @@ -387,28 +387,38 @@ let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1, } // Section B.1 - Load Integer Instructions, p. 90 -defm LDSB : Load<"ldsb", 0b001001, sextloadi8, IntRegs, i32>; -defm LDSH : Load<"ldsh", 0b001010, sextloadi16, IntRegs, i32>; -defm LDUB : Load<"ldub", 0b000001, zextloadi8, IntRegs, i32>; -defm LDUH : Load<"lduh", 0b000010, zextloadi16, IntRegs, i32>; -defm LD : Load<"ld", 0b000000, load, IntRegs, i32>; +let DecoderMethod = "DecodeLoadInt" in { + defm LDSB : Load<"ldsb", 0b001001, sextloadi8, IntRegs, i32>; + defm LDSH : Load<"ldsh", 0b001010, sextloadi16, IntRegs, i32>; + defm LDUB : Load<"ldub", 0b000001, zextloadi8, IntRegs, i32>; + defm LDUH : Load<"lduh", 0b000010, zextloadi16, IntRegs, i32>; + defm LD : Load<"ld", 0b000000, load, IntRegs, i32>; +} // Section B.2 - Load Floating-point Instructions, p. 92 -defm LDF : Load<"ld", 0b100000, load, FPRegs, f32>; -defm LDDF : Load<"ldd", 0b100011, load, DFPRegs, f64>; -defm LDQF : Load<"ldq", 0b100010, load, QFPRegs, f128>, - Requires<[HasV9, HasHardQuad]>; +let DecoderMethod = "DecodeLoadFP" in + defm LDF : Load<"ld", 0b100000, load, FPRegs, f32>; +let DecoderMethod = "DecodeLoadDFP" in + defm LDDF : Load<"ldd", 0b100011, load, DFPRegs, f64>; +let DecoderMethod = "DecodeLoadQFP" in + defm LDQF : Load<"ldq", 0b100010, load, QFPRegs, f128>, + Requires<[HasV9, HasHardQuad]>; // Section B.4 - Store Integer Instructions, p. 95 -defm STB : Store<"stb", 0b000101, truncstorei8, IntRegs, i32>; -defm STH : Store<"sth", 0b000110, truncstorei16, IntRegs, i32>; -defm ST : Store<"st", 0b000100, store, IntRegs, i32>; +let DecoderMethod = "DecodeStoreInt" in { + defm STB : Store<"stb", 0b000101, truncstorei8, IntRegs, i32>; + defm STH : Store<"sth", 0b000110, truncstorei16, IntRegs, i32>; + defm ST : Store<"st", 0b000100, store, IntRegs, i32>; +} // Section B.5 - Store Floating-point Instructions, p. 97 -defm STF : Store<"st", 0b100100, store, FPRegs, f32>; -defm STDF : Store<"std", 0b100111, store, DFPRegs, f64>; -defm STQF : Store<"stq", 0b100110, store, QFPRegs, f128>, - Requires<[HasV9, HasHardQuad]>; +let DecoderMethod = "DecodeStoreFP" in + defm STF : Store<"st", 0b100100, store, FPRegs, f32>; +let DecoderMethod = "DecodeStoreDFP" in + defm STDF : Store<"std", 0b100111, store, DFPRegs, f64>; +let DecoderMethod = "DecodeStoreQFP" in + defm STQF : Store<"stq", 0b100110, store, QFPRegs, f128>, + Requires<[HasV9, HasHardQuad]>; // Section B.9 - SETHI Instruction, p. 104 def SETHIi: F2_1<0b100, |